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| DATA SHEET MOS INTEGRATED CIRCUIT PD17240,17241,17242,17243,17244,17245,17246 4-BIT SINGLE-CHIP MICROCONTROLLERS FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTERS DESCRIPTION The PD17240, 17241, 17242, 17243, 17244, 17245, 17246 (hereafter called the PD17246 Subseries) are 4bit single-chip microcontrollers for small general-purpose infrared remote control transmitters. This subseries employs 17K general-purpose register system architecture for the CPU, and can directly execute operations between data memories instead of the conventional method of executing operations through an accumulator. Moreover, all the instructions are 16-bit/1-word instructions, enabling efficient programming. In addition, a one-time PROM model, the PD17P246, to which data can be written only once, is also available. This product is convenient either for evaluating the PD17246 Subseries programs or for small-scale production of application systems. Detailed function descriptions are provided in the following user's manual. Be sure to read them before designing. PD172xx Subseries User's Manual: U12795E FEATURES * Infrared remote controller carrier generator (REM output) * 17K architecture: General-purpose register system * Program memory (ROM), data memory (RAM) PD17240 Program 4 KB 447 x 4 bits memory (ROM) (2,048 x 16) Data memory (RAM) PD17241 8 KB (4,096 x 16) PD17242 12 KB (6,144 x 16) PD17243 16 KB (8,192 x 16) PD17244 20 KB PD17245 24 KB PD17246 32 KB (10,240 x 16) (12,288 x 16) (16,384 x 16) * 8-bit timer: 1 channel * Basic interval timer/watchdog timer: 1 channel * Instruction execution time (can be changed in two steps) @ fX = 4 MHz: * External interrupt pin (INT/P1B0): * I/O pins: * Supply voltage: * On-chip RAM retention detector * Low-voltage detector (mask option) Unless otherwise specified, the PD17246 is treated as the representative model throughout this document. 4 s (high-speed mode)/8 s (normal mode) 1 24 VDD = 2.0 to 3.6 V The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. U15002EJ1V0DS00 (1st edition) Date Published April 2003 N CP (K) Printed in Japan The mark shows major revised points. c PD17240, 17241, 17242, 17243, 17244, 17245, 17246 APPLICATIONS Preset remote controllers, toys, portable systems, etc. ORDERING INFORMATION Part Number Package 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) PD17240MC-xxx-5A4 PD17241MC-xxx-5A4 PD17242MC-xxx-5A4 PD17243MC-xxx-5A4 PD17244MC-xxx-5A4 PD17245MC-xxx-5A4 PD17246MC-xxx-5A4 Remark xxx indicates ROM code suffix. 2 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 DIFFERENCES BETWEEN PD17246 SUBSERIES, PD17236 SUBSERIES, AND PD17255 SUBSERIES (1/2) Item ROM PD17246 Subseries PD17240: PD17241: PD17242: PD17243: PD17244: PD17245: PD17246: 447 x 4 bits 2,048 4,096 6,144 8,192 x x x x 16 16 16 16 bits bits bits bits PD17236 Subseries PD17230: PD17231: PD17232: PD17233: PD17234: PD17235: PD17236: 223 x 4 bits 2,048 4,096 6,144 8,192 x x x x 16 16 16 16 bits bits bits bits PD17225 Subseries PD17225: PD17226: PD17227: PD17228: 2,048 4,096 6,144 8,192 x x x x 16 16 16 16 bits bits bits bits 10,240 x 16 bits 12,288 x 16 bits 16,384 x 16 bits 10,240 x 16 bits 12,288 x 16 bits 16,384 x 16 bits 111 x 4 bits (PD17225, 17226) 223 x 4 bits (PD17227, 17228) P0B0 to P0B3: Input P0C0 to P0C3: Output P0D0 to P0D3: Output RAM Ports P0B0 to P0B3: I/O (bit I/O) P0C0 to P0C3: I/O (group I/O) P0D0 to P0D3: I/O (group I/O) P1A0 to P1A2: I/O (bit I/O) P1B0: I/O, functions alternately as INT pin P0B0 to P0B3: I/O (bit I/O) P0C0 to P0C3: I/O (group I/O) P0D0 to P0D3: I/O (group I/O) P1A0: Input or output selectable by mask option Reset * Reset by watchdog timer * Reset by stack pointer * Low-voltage detector (mask option) The RESET pin is internally pulled down by the occurrence of the internal reset signals on the left, causing a reset (usually, the RESET pin is pulled up). A low level is output from the WDOUT pin by the occurrence of the internal reset signals on the left, and a reset takes place if the WDOUT pin is externally connected to the RESET pin. Capacitor for oscillation Vector address Selected by mask option (15 pF) Basic interval timer: 0002H Rising and falling edges of INT pin: 0003H 8-bit timer: 0004H Provided Not provided Basic interval timer: 0001H Rising and falling edges of INT pin: 0002H 8-bit timer: 0003H RAM retention flag Not provided Data Sheet U15002EJ1V0DS 3 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 DIFFERENCES BETWEEN PD17246 SUBSERIES, PD17236 SUBSERIES, AND PD17255 SUBSERIES (2/2) Item STOP mode release condition PD17246 Subseries <1> When any of pins P0A0 to P0A3 goes low <2> When pins P0B0 to P0B3, P0C0 to P0C3, and P0D0 PD17236 Subseries PD17225 Subseries <1> When any of pins P0A0 When any of pins P0A0 to to P0A3 goes low P0A3 and P0B0 to P0B3 goes <2> When pins P0B0 to P0B3, low P0C0 to P0C3, and P0D0 to P0D3 are used as input to P0D3 are used as pins and when any of input pins and when any them goes low of them goes low <3> When an interrupt <3> When an interrupt request (IRQ) of the request (IRQ) of the interrupt for which the IP interrupt for which the IP flag is set is generated at flag is set is generated the rising edge or falling at the rising edge or edge of the INT pin falling edge of the INT <4> When P0E0 to P0E3 are pin used as input pins when a key matrix is used and when any of these pins goes low <5> When P1A0 to P1A2 and P1B0 are used as input pins when a key matrix is used and when the level of any of these pins equals the set clear level Carrier frequency (fX = 4 MHz) Selected by register file (after reset: fX/2) <1> If carrier generation clock is fX/2: 3.9 kHz to 1 MHz <2> If carrier generation clock is fX: 7.8 kHz to 2 MHz <3> If carrier generation clock is 2fX: 15.6 kHz to 4 MHz * NRZLTMM: 8 bits (REM output control bit is bit 1 of register file at address 12H) * NRZHTMM: 8 bits Selected by mask option <1> If carrier generation clock is fX/2: 7.8 kHz to 1 MHz <2> If carrier generation clock is fX: 15.6 kHz to 2 MHz 7.8 kHz to 1 MHz NRZ low-level period setting modulo register (NRZLTMM) and NRZ high-level period setting modulo register (NRZHTMM) * NRZLTMM: 7 bits (bit 7 is REM output control bit) * NRZHTMM: 7 bits (bit 7 is fixed to 0) 4 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 PIN CONFIGURATION (TOP VIEW) * 30-pin plastic SSOP (7.62 mm (300)) PD17240MC-xxx-5A4, 17241MC-xxx-5A4, 17242MC-xxx-5A4, 17243MC-xxx-5A4, PD17244MC-xxx-5A4, 17245MC-xxx-5A4, 17246MC-xxx-5A4 P0D2 P0D3 P1B0/INT P0E0 P0E1 P0E2 P0E3 REM VDD XOUT XIN GND RESET P1A0 P1A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P1A2 P0D1 P0D0 P0C3 P0C2 P0C1 P0C0 P0B3 P0B2 P0B1 P0B0 P0A3 P0A2 P0A1 P0A0 GND: INT: Ground External interrupt request signal input P0A0 to P0A3: Input port (CMOS input with pull-up resistor) P0B0 to P0B3: I/O port (CMOS input with pull-up resistor/N-ch open-drain output) P0C0 to P0C3: I/O port (CMOS input with pull-up resistor/N-ch open-drain output) P0D0 to P0D3: I/O port (CMOS input with pull-up resistor/N-ch open-drain output) P0E0 to P0E3: I/O port (when key matrix is used: CMOS input with pull-up resistor/N-ch opendrain output, when key matrix is not used: CMOS input/push-pull output) P1A0/P1A2: P1B0: REM: RESET: VDD: XIN, XOUT: Input port (when key matrix is used: CMOS input/N-ch open-drain output, when key matrix is not used: CMOS input/push-pull output) Input port (CMOS input) Remote controller output (CMOS push-pull output) Reset input Power supply Resonator connection Data Sheet U15002EJ1V0DS 5 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 BLOCK DIAGRAM P0A0 P0A1 P0A2 P0A3 P0A RF Remote control divider REM RAM 447 x 4 bits P0B0 P0B1 P0B2 P0B3 System registers 8-bit timer P0B Interrupt controller ALU INT/P1B0 P0C0 P0C1 P0C2 P0C3 Reset controller P0C ROM PD17240: 2,048 x 16 bits PD17241: 4,096 x 16 bits PD17242: 6,144 x 16 bits PD17243: 8,192 x 16 bits PD17244: 10,240 x 16 bits PD17245: 12,288 x 16 bits PD17246: 16,384 x 16 bits RESET Instruction decoder P0D0 P0D1 P0D2 P0D3 P0D Program counter P0E0 P0E1 P0E2 P0E3 Power supply circuit CPU clock VDD GND P0E Stack (5 levels) P1A0 P1A1 P1A2 P1A Basic interval/ watchdog timer XIN OSC XOUT P1B0 P1B 6 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 CONTENTS 1. PIN FUNCTIONS .......................................................................................................................... 1.1 Pin Function List ............................................................................................................... 1.2 I/O Circuits ......................................................................................................................... 1.3 Handling of Unused Pins ................................................................................................. MEMORY SPACE ......................................................................................................................... 2.1 Program Counter (PC) ...................................................................................................... 2.2 Program Memory (ROM) .................................................................................................. 2.3 Stack ................................................................................................................................... 2.4 Data Memory (RAM) .......................................................................................................... 2.5 Register File (RF) .............................................................................................................. PORTS .......................................................................................................................................... 3.1 Port 0A (P0A0 to P0A3) ..................................................................................................... 3.2 Port 0B (P0B0 to P0B3) ..................................................................................................... 3.3 Port 0C (P0C0 to P0C3) ..................................................................................................... 3.4 Port 0D (P0D0 to P0D3) ..................................................................................................... 3.5 Port 0E (P0E0 to P0E3) ...................................................................................................... 3.6 Port 1A (P1A0 to P1A2) ..................................................................................................... 3.7 Port 1B (P1B0).................................................................................................................... 3.8 INT Pin ................................................................................................................................ 3.9 Switching Bit I/O (Port 0B, 0E, 1A) ................................................................................. 3.10 Selecting I/O Mode of Group I/O (Port 0C, 0D) ............................................................. 3.11 Selecting Whether Key Matrix Is Used or Not (Port 0E, 1A) ....................................... 3.12 Specifying Resistor Connection (Port 0E, 1A) ............................................................. 3.13 Selecting Standby Mode Release Condition and Whether Pull-Up or Pull-Down Resistor Is Connected (Port 1A) ..................................................................................... 3.14 Selecting Whether Key Matrix Is Used, Standby Mode Release Condition, and Whether Pull-Up or Pull-Down Resistor Is Connected (Port 1B) ............................... CLOCK GENERATOR ................................................................................................................. 4.1 Instruction Execution Time (CPU Clock) Selection ...................................................... 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR ................................... 5.1 Configuration of 8-Bit Timer (with Modulo Function) .................................................. 5.2 Function of 8-Bit Timer (with Modulo Function) .......................................................... 5.3 Carrier Generator for Remote Controller ....................................................................... BASIC INTERVAL TIMER/WATCHDOG TIMER ......................................................................... 6.1 Source Clock for Basic Interval Timer ........................................................................... 6.2 Controlling Basic Interval Timer ..................................................................................... 6.3 Operation Timing for Watchdog Timer ........................................................................... RAM RETENTION DETECTOR ................................................................................................... 7.1 RAM Retention Flag .......................................................................................................... 9 9 12 14 15 15 18 20 22 31 34 34 34 34 34 35 35 36 37 38 40 41 42 44 46 47 47 48 48 50 51 57 57 57 59 60 60 2. 3. 4. 5. 6. 7. Data Sheet U15002EJ1V0DS 7 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 8. INTERRUPT FUNCTIONS ........................................................................................................... 8.1 Interrupt Sources .............................................................................................................. 8.2 Hardware of Interrupt Controller .................................................................................... 8.3 Interrupt Sequence ........................................................................................................... STANDBY FUNCTIONS ............................................................................................................... 9.1 HALT Mode ......................................................................................................................... 9.2 HALT Instruction Execution Conditions ........................................................................ 9.3 STOP Mode ........................................................................................................................ 9.4 STOP Instruction Execution Conditions ........................................................................ 9.5 Releasing Standby Mode ................................................................................................. 62 62 63 66 68 68 69 70 71 72 73 73 73 74 75 76 76 77 83 83 84 85 87 88 94 95 96 97 98 9. 10. RESET .......................................................................................................................................... 10.1 Reset by Reset Signal Input ............................................................................................ 10.2 Reset by Watchdog Timer (with RESET Pin Internally Pulled Down) ........................ 10.3 Reset by Stack Pointer (with RESET Pin Internally Pulled Down) ............................. 11. LOW-VOLTAGE DETECTOR (WITH RESET PIN INTERNALLY PULLED DOWN) ................. 12. ASSEMBLER RESERVED WORDS ............................................................................................ 12.1 Mask Option Directives .................................................................................................... 12.2 Reserved Symbols ............................................................................................................ 13. INSTRUCTION SET ..................................................................................................................... 13.1 Instruction Set Outline ..................................................................................................... 13.2 Legend ................................................................................................................................ 13.3 List of Instructions ........................................................................................................... 13.4 Assembler (RA17K) Embedded Macro Instructions .................................................... 14. ELECTRICAL SPECIFICATIONS ................................................................................................ 15. APPLICATION CIRCUIT EXAMPLE ........................................................................................... 16. PACKAGE DRAWING ................................................................................................................. 17. RECOMMENDED SOLDERING CONDITIONS ........................................................................ APPENDIX A DIFFERENCES BETWEEN PD17246 AND PD17P246 ....................................... APPENDIX B DEVELOPMENT TOOLS ............................................................................................ 8 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 1. 1.1 PIN FUNCTIONS Pin Function List (1/3) Pin Name P0D0 P0D1 P0D2 P0D3 Function These pins constitute a 4-bit I/O port which can be set to the input Output Format After Reset N-ch Low-level output Pin No. 28 29 1 2 or output mode in 4-bit units (group I/O). open drain In the input mode, these pins serve as CMOS input pins with a pull-up resistor, and can be used to input the key return signals of a key matrix. The standby status must be released when at least one of the input lines goes low. In the output mode, these pins are used as N-ch open-drain output pins and can be used to output the signals of a key matrix. This is an input port pin. Whether this pin functions as the P1B0 pin or the INT pin can be selected by the register file. * P1B0 This is a 1-bit CMOS input port. This port can be used to input key return signals when a key matrix is used. At this time, whether a pull-up/down resistor is connected to this port and the standby mode release condition (whether it is released when this pin is high or low) can be selected. 1. If connection of a resistor is specified and if it is specified that the standby mode is released when this pin goes low ... A pull-up resistor is connected. If a low level is input to the P1B0 pin, the standby mode is released. 2. If connection of a resistor is specified and if it is specified that the standby mode is released when this pin goes high ... A pull-down resistor is connected. If a high level is input to the P1B0 pin, the standby mode is released. 3. If connection of a resistor is not specified and if it is specified that the standby mode is released when this pin goes low (or high) ... No resistor is connected. If a low (or high) level is input to the P1B0 pin, the standby mode is released. If a key matrix is not used, whether a resistor is connected and whether the resistor is pull-up or pull-down can be selected. * INT This is an external interrupt request signal. It can also be used to release the standby mode if an external interrupt request signal is input to this pin while the INT pin interrupt enable flag (IP) is set. - 3 P1B0/INT P1B0 input (when key matrix not used and no resistor connected) Data Sheet U15002EJ1V0DS 9 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 1.1 Pin Function List (2/3) Pin Name P0E0 P0E1 P0E2 P0E3 Function These pins constitute a 4-bit I/O port that can be set to the input or output mode in 1-bit units. If this port is set to the input mode when a key matrix is used, it functions as a CMOS input port with a pull-up resistor and can be used to input key return signals. If one of the pins of this port goes low, the standby mode is released. If this port is set to the output mode when a key matrix is used, it functions as an N-ch open-drain output port and can be used to output key matrix signals. If this port is set to the input mode when a key matrix is not used, it functions as a CMOS input port to/from which a resistor can be connected/disconnected in 1-bit units. If this port is set in the output mode when a key matrix is not used, it functions as a highcurrent CMOS output port. 8 REM Outputs transfer signal for infrared remote controller. Active-high output. Power supply Connects ceramic resonator for system clock oscillation. A capacitor (15 pF) for oscillation can be connected by using a mask option. Ground System reset input. Turns ON pull down resistor if the POC or watchdog timer overflows and if the stack pointer overflows or underflows, and resets the system. Usually, the pull-down resistor is ON. CMOS push-pull - - Low-level output - (Oscillation stops) Output Format After Reset When key matrix is used: N-ch open-drain, when key matrix is not used: CMOS push-pull CMOS input (when key matrix is not used and no resistor connected) Pin No. 4 5 6 7 9 10 11 VDD XOUT XIN 12 13 GND RESET - - Input - 10 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 1.1 Pin Function List (3/3) Pin Name P1A0 P1A1 P1A2 Function These pins constitute a 3-bit I/O port that can be set to the input or output mode in 1-bit units. If this port is set to the input mode when a key matrix is used, it functions as a CMOS input port and can be used to input key return signals. At this time, whether a pull-up/down resistor is connected to this port and the standby mode release condition (whether it is released when this pin is high or low) can be selected in 1-bit units 1. If connection of a resistor is specified and if it is specified that the standby mode is released when this port goes low ... A pull-up resistor is connected. If a low level is input to the set key, the standby mode is released. 2. If connection of a resistor is specified and if it is specified that the standby mode is released when this port goes high ... A pull-down resistor is connected. If a high level is input to the set key, the standby mode is released. 3. If connection of a resistor is not specified and if it is specified that the standby mode is released when this port goes low (or high) ... No resistor is connected. If a low (or high) level is input to the set key, the standby mode is released. If this port is set to the output mode when a key matrix is used, it functions as an N-ch open-drain output port and can be used to output key matrix signals. If this port is set to the input mode when a key matrix is used, it functions as a CMOS input port. Connection of a resistor to this port and whether the resistor is pull-up or pull-down can be selected in 1-bit units. If this port is set in the output mode when a key matrix is not used, it functions as a high-current CMOS output port. 16 17 18 19 20 21 22 23 P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 These pins are CMOS input pins with a 4-bit pull-up resistor. They can be used to input the key return signals of a key matrix. If any one of these pins goes low, the standby status is released. - CMOS input with pull-up resistor Output Format After Reset When key matrix is used: N-ch open-drain, when key matrix is not used: CMOS push-pull. CMOS input (when key matrix is not used and no resistor connected) Pin No. 14 15 30 These pins constitute a 4-bit I/O port that can be set to the input or N-ch output mode in 1-bit units. open drain In the input mode, these pins are CMOS input pins with a pull-up resistor, and can be used to input the key return signals of a key matrix. The standby status is released when at least one of these pins goes low. In the output mode, they serve as N-ch open-drain output pins and can be used to output the key return signals of a key matrix. These pins constitute a 4-bit I/O port that can be set to the input or N-ch output mode in 4-bit units (group I/O). open drain In the input mode, these pins are CMOS input pins with a pull-up resistor, and can be used to input the key return signals of a key matrix. The standby status is released when at least one of these pins goes low. In the output mode, they serve as N-ch open-drain output pins and can be used to output the key return signals of a key matrix. CMOS input with pull-up resistor 24 25 26 27 P0C0 P0C1 P0C2 P0C3 Low-level output Data Sheet U15002EJ1V0DS 11 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 1.2 I/O Circuits The equivalent I/O circuit for each PD17246 pin is shown below. Figure 1-1. I/O Circuits (1/2) (1) P0A VDD (4) P1A Data STOP clear level VDD Input buffer Data Data Pull-up/ pull-down resistor P-ch VDD P-ch (2) P0B, P0C, P0D Output latch Key matrix VDD Data use/nonuse resistor Output disable Selector Input buffer N-ch N-ch P-ch Data Output latch (5) P1B VDD Output disable Selector Input buffer N-ch Data Pull-up/ pull-down resistor P-ch (3) P0E VDD Data Data Data Output disable Selector Input buffer Key matrix use/nonuse resistor Data STOP clear level N-ch Selector Input buffer Pull-up resistor Output latch VDD P-ch P-ch N-ch 12 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Figure 1-1. I/O Circuits (2/2) (6) RESET VDD (8) REM VDD Data P-ch Reset input P-ch Output disable N-ch Input buffer Schmitt trigger input with hysteresis characteristics N-ch (7) INT Input buffer Schmitt trigger input with hysteresis characteristics Data Sheet U15002EJ1V0DS 13 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 1.3 Handling of Unused Pins Handle the unused pins as follows. Table 1-1. Handling of Unused Pins Pin Name P0A0 to P0A3 P0B0 to P0B3 P0C0 to P0C3 P0D0 to P0D3 P0E0 to P0E3 P1A0 to P1A2 P1B0/INT REM Connect to GND. Leave open. Connect to GND (When input). Leave open. Recommended Connection 14 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 2. 2.1 MEMORY SPACE Program Counter (PC) The program counter (PC) specifies an address of the program memory (ROM). The program counter consists of an 11/12/13-bit binary counter and a 1-bit segment register (SGR) as shown in Figure 2-1. Its contents are initialized to address 0000H at reset. Figure 2-1. Configuration of Program Counter Page MSB SGR PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 LSB PC0 PC (PD17240) PC (PD17241) PC (PD17242, 17243) PC (PD17244, 17245, 17246) 2.1.1 Segment register (SGR) The segment register specifies a segment of the program memory. Table 2-1 shows the relationship between the segment register and program memory. Table 2-1. Relationship Between Segment Register and Program Memory Value of Segment Register 0 1 Segment of Program Memory Segment 0 Segment 1 The segment register is set when the following instructions are executed. * BR @AR * CALL @AR * SYSCAL entry Data Sheet U15002EJ1V0DS 15 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 The first address of the subroutine that can be called by the system call instruction ("SYSCAL entry") is the first 16 steps of each block (blocks 0 to 7) in page 0 of segment 1 (system segment). Figure 2-2. Outline of System Call Instruction Segment 0 00000H 02000H Segment 1 (system segment) 02000H Block 0 0 2 0FFH 02100H Block 1 0 2 1FFH 02200H Block 2 0 2 0 0FH Block 0 of segment 1 Entry address of SYSCAL instruction Page 0 (16 bits x 2K steps) 0 2 2FFH . . . . 02700H Block 7 Area in which entry address of system segment can be specified 0 0 7FFH 00800H Page 1 0 0FFFH 01000H Page 2 0 1 7FFH 01800H Page 3 0 1FFFH (16 bits x 8K steps) 0 2 7FFH 02800H Page 1 0 2FFFH 03000H Page 2 0 3 7FFH 03800H Page 3 0 3FFFH (16 bits x 8K steps) 16 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Figure 2-3. Value of Program Counter on Execution of Each Instruction Contents of Program Counter (PC)Note SGR b12 Page 0 Page 1 Page 2 Page 3 CALL addr Retained Retained Program Counter Instruction BR addr b11 0 1 0 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 1 0 Operand of instruction (addr) 1 0 Operand of instruction (addr) SYSCAL entry 1 BR @AR CALL @AR Contents of address register MOVT DBF, @AR RET RETSK RETI Other instructions (including skip instruction) On acknowledging interrupt 0 Vector address of each interrupt Retained 0 0 entryH 0 0 0 0 entryL Contents (return address) of address stack register (ASR) specified by stack pointer (SP) Increment Watchdog timer reset, RESET pin, reset by stack pointer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note PD17240: PD17241: PD17242, 17243: b0 to b10 b0 to b11 b0 to b12 PD17244, 17245, 17246: b0 to b12, SGR Remark entryH: Higher 3 bits of entry entryL: Lower 4 bits of entry Table 2-2. Interrupt Vector Address Priority 1 2 3 Internal/External Internal External Internal Interrupt Source 8-bit timer Rising and falling edges of INT pin Basic interval timer 0004H 0003H 0002H Vector Address Data Sheet U15002EJ1V0DS 17 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 2.2 Program Memory (ROM) The configuration of the program memory is as follows. Part Number Program Memory Capacity 2,048 x 16 bits 4,096 x 16 bits 6,144 x 16 bits 8,192 x 16 bits 10,240 x 16 bits 12,288 x 16 bits 16,384 x 16 bits Program Memory Address 0000H to 07FFH 0000H to 0FFFH 0000H to 17FFH 0000H to 1FFFH 0000H to 27FFH 0000H to 2FFFH 0000H to 3FFFH PD17240 PD17241 PD17242 PD17243 PD17244 PD17245 PD17246 The program memory stores the program, interrupt vector table, and fixed data table. The program memory is addressed by the program counter. Figure 2-4 shows the program memory map. The entire range of the program memory can be addressed by the BD addr, BR @AR, CALL @AR, MOVT DBF, and @AR instructions. Note, however, that the subroutine entry addresses that can be specified by the CALL addr instruction are from 0000H to 07FFH. 18 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Figure 2-4. Program Memory Map Address 0 0 0 0 H Reset start address 0 0 0 1 H Normal address 0 0 0 2 H Basic interval timer interrupt vector 0 0 0 3 H INT pin rising/falling edge interrupt vector 0 0 0 4 H 8-bit timer interrupt vector 0 7 FFH ( PD17240) Segment 0 Branch addresses for BR addr Page 1 instruction Page 2 1 7 FFH ( PD17242) Page 3 1 FFFH 2000H ( PD17243) Page 0 ( PD17244) Page 1 2 FFFH ( PD17245) Segment 1 Branch (system addresses segment) for BR addr Page 2 instruction Subroutine entry address for CALL addr instruction Page 0 Subroutine entry Branch addresses for address for CALL BR@AR instruction addr instruction Subroutine entry addresses for CALL@AR instruction Table reference addresses for MOVT DBF, @AR instruction 0 FFFH ( PD17241) 2 7 FFH Page 3 3 FFFH ( PD17246) 16 bits Data Sheet U15002EJ1V0DS 19 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 2.3 Stack A stack is a register used to save a program return address and the contents of system registers (to be described later) when a subroutine is called or when an interrupt is acknowledged. 2.3.1 Stack configuration Figure 2-5 shows the stack configuration. A stack consists of a stack pointer (a 4-bit binary counter, the highest bit fixed to 0), five 11-bit (PD17240)/12bit (PD17241)/13-bit (PD17242, 17243)/14-bit (PD17244, 17245, 17246) address stack registers, and three 6bit interrupt stack registers. Figure 2-5. Stack Configuration Stack pointer (SP) b3 0 b2 b1 b0 0H 1H 2H 3H 4H 5H The RESET pin is internally pulled down and reset is effected. 6H 7H b13 b12 b11 b10 b9 Address stack registers (ASR) b8 b7 b6 b5 b4 b3 b2 b1 b0 SPb2 SPb1 SPb0 Address stack register 0 Address stack register 1 Address stack register 2 Address stack register 3 Address stack register 4 Undefined Undefined Undefined PD17240 PD17241 PD17242, 17243 PD17244, 17245, 17246 Interrupt stack registers (INTSK) b5 0H BANKSK0 1H 2H BANKSK1 BANKSK2 b4 BCDSK0 BCDSK1 BCDSK2 b3 CMPSK0 CMPSK1 CMPSK2 b2 CYSK0 CYSK1 CYSK2 b1 ZSK0 ZSK1 ZSK2 b0 IXESK0 IXESK1 IXESK2 20 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 2.3.2 Function of stack The address stack register stores a return address when the subroutine call instruction or table reference instruction (first instruction cycle) is executed or when an interrupt is acknowledged. It also stores the contents of the address registers (ARs) when a stack manipulation instruction (PUSH AR) is executed. If subroutines or interrupts are nested to more than 5 levels, the RESET pin is internally pulled down and a reset is effected. The interrupt stack register (INTSK) saves the contents of the bank register (BANK) and program status word (PSWORD) when an interrupt is acknowledged. The saved contents are restored when an interrupt return (RETI) instruction is executed. INTSK saves data each time an interrupt is acknowledged, but the data stored first is lost if more than 3 levels of interrupts occur. 2.3.3 Stack pointer (SP) and interrupt stack pointer Table 2-3 shows the operations of the stack pointer (SP). The stack pointer can take eight values, 0H to 7H. Because there are only five stack registers available, however, the RESET pin is internally pulled down and reset is effected if the value of SP is 6 or greater. Table 2-3. Operations of Stack Pointer Instruction CALL addr CALL @AR MOVT DBF, @AR (1st instruction cycle) PUSH AR SYSCAL entry When interrupt is acknowledged RET RETSK MOVT DBF, @AR (2nd instruction cycle) POP AR RETI -1 +1 -1 0 Value of Stack Pointer (SP) -1 Counter of Interrupt Stack Register 0 +1 +1 Data Sheet U15002EJ1V0DS 21 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 2.4 Data Memory (RAM) The data memory (RAM) stores data for operations and control. It can always be read/written by instructions. 2.4.1 Memory configuration Figure 2-6 shows the configuration of the data memory (RAM). The data memory consists of four "banks": BANK0, BANK1, BANK2, and BANK3. In each bank, every 4 bits of data are assigned an address. The higher 3 bits of the address indicate a "row address" and the lower 4 bits of the address indicate a "column address". For example, a data memory location indicated by row address 1H and column address 0AH is termed a data memory location at address 1AH. Each address stores data of 4 bits (= 1 nibble). In addition, the data memory is divided into the following six functional blocks. (1) System register (SYSREG) A system register (SYSREG) is resident on addresses 74H to 7FH (12 nibbles) of each bank. In other words, each bank has the same system register at its addresses 74H to 7FH. (2) Data buffer (DBF) A data buffer is resident on addresses 0CH to 0FH (4 nibbles) of bank 0 of the data memory. The reset value is 0320H. (3) General register (GR) A general register is resident on any row (16 nibbles) of any bank of the data memory. The row address of the general register is pointed to by the general register pointer (RP) in the system register (SYSREG). (4) Port register A port data register is resident on addresses 6FH, and 70H to 73H of BANK0 and addresses 70H and 71H of BANK1 (7 nibbles) of the data memory. No data can be written to or read from addresses 72H and 73H of BANK1 and addresses 70H to 73H of BANK2 or BANK3. 22 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 (5) General-purpose data memory The general-purpose data memory area is an area of the data memory excluding the system register area, and the port register area. This memory area has a total of 447 nibbles (111 nibbles in BANK0 and 336 nibbles (112 nibbles x 3) in BANK1 to BANK3). Figure 2-6. Configuration of Data Memory (1/2) Column address 0 0 1 Row address BANK 0 6 7 8 9 A B C D E F 1 2 3 4 5 Data buffer (DBF) 2 3 4 5 6 7 P0A P0B P0C P0D System register (SYSREG) P0E Example Address 1AH in BANK 0 0 0 1 Row address 1 Column address 2 3 4 5 6 BANK 1 7 8 9 A B C D E F 2 3 4 5 6 7 P1A P1B Note 2 Note 3 Note 1 System register (SYSREG) Notes 1. Address 6FH of BANK1 can be used as a general-purpose data memory area. 2. Bits 0 to 2 of address 70H of BANK1 are used. Bit 3 is fixed to 0. 3. Only bit 0 of address 71H of BANK1 is used. Bits 1 to 3 are fixed to 0. Caution No data can be written to or read from addresses 72H and 73H of BANK1. Data Sheet U15002EJ1V0DS 23 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Figure 2-6. Configuration of Data Memory (2/2) 0 0 1 Row address 1 Column address 2 3 4 5 6 BANK2 7 8 9 A B C D E F 2 3 4 5 6 System register (SYSREG) Note 0 0 1 Row address 1 Column address 2 3 4 5 6 BANK3 7 8 9 A B C D E F 2 3 4 5 6 System register (SYSREG) Note Note Address 6FH of BANK2, BANK3 can be used as a general-purpose data memory area. Caution No data can be written to or read from addresses 70H to 73H of BANK2 and BANK3. 24 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 2.4.2 System registers (SYSREG) The system registers are registers that are directly related to control of the CPU. These registers are mapped to addresses 74H to 7FH on the data memory and can be referenced regardless of bank specification. The system registers include the following registers. * Address registers (AR0 to AR3) * Window register (WR) * Bank register (BANK) * Memory pointer enable flag (MPE) * Memory pointers (MPH, MPL) * Index registers (IXH, IXM, IXL) * General register pointers (RPH, RPL) * Program status word (PSWORD) Figure 2-7. Configuration of System Registers Address 74H 75H 76H 77H 78H 79H 7AH 7BH Index register (IX) 7CH 7DH General register pointer (RP) 7EH 7FH Program status word (PSWORD) Name Address register (AR) Window Bank register register (WR) (BANK) Data memory row address pointer (MP) IXH MPH IXM MPL IXL Symbol Bit AR 3 AR 2 AR 1 AR 0 WR BANK RPH RPL PSW b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 00 (AR) ( PD17244,17245,17246) (AR) ( PD17242,17243) (AR) ( PD17241) (AR) ( PD17240) (WR) (BANK) M 00 P00 E (IX) 00 (MP) (RP) BCC I CMY Z X DP E Data 000 0000 00000 Initial value at reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Undefined 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data Sheet U15002EJ1V0DS 25 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 2.4.3 General register (GR) A general register is a register on the data memory and used for arithmetic operations and transfer of data to and from the data memory. (1) Configuration of general register Figure 2-8 shows the configuration of the general registers. A general register occupies 16 nibbles (16 x 4 bits) on a selected row address of the data memory as shown in Figure 2-8. The row address is selected by the general register pointer (RP) of the system register. Five bits of RP are valid. Of these, the lower 3 bits (bits 1 to 3 of RPL) are used to set a row address, and the higher 2 bits (bits 0 and 1 of RPH) are used to set a bank. The data memory that can be used as general registers is at row addresses 0H to 7H in BANK0 to 4. (2) Functions of general registers A general register enables an arithmetic operation and data transfer between the data memory and a selected general register by a single instruction. As a general register is a part of the data memory, you can say that the general registers enable arithmetic operations and data transfer between two locations of the data memory. Similarly, the general registers can be accessed by a data memory manipulation instruction as they are a part of the data memory. 26 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Figure 2-8. Configuration of General Registers General register pointer (RP) RPH RPL BANK0 0 0 1 2 3 4 5 6 7 Port register BANK1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 Port 7 register BANK2 Port register Column address 2 3 4 5 6 7 8 9 A B C D E F b3 b2 b1 b0 b3 b2 b1 b0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 Assigned to BCD flag Fixed to 0 Fixed to 0 0 0 0 0 0 General register (16 nibbles) Example General registers when RP = 0000010B System register RP System register 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 BANK3 System register Same system registers exist General register settable range 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 System register Setting of BANK Setting of row address Data Sheet U15002EJ1V0DS 27 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 2.4.4 Data buffer (DBF) The data buffer on addresses 0CH to 0FH of the data memory is used for data transfer to and from peripheral hardware and for storage of data during table referencing. (1) Functions of the data buffer The data buffer has two major functions: a function to transfer data to and from hardware and a function to read constant data from the program memory (for table referencing). Figure 2-9 shows the relationship between the data buffer and peripheral hardware. Figure 2-9. Data Buffer and Peripheral Hardware Data buffer (DBF) Peripheral address Internal bus 05H, 06H Peripheral hardware 8-bit timer (TMC, TMM) Carrier generator for remote controller (NRZLTMM, NRZHTMM) Address register (AR) 03H, 04H 40H Program memory (ROM) Constant data 28 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Table 2-4. Relationship Between Peripheral Hardware and Data Buffer Peripheral Hardware 8-bit timer Name 8-bit counter 8-bit modulo register Remote controller carrier generator NRZ low-level timer modulo register NRZ high-level timer modulo register Address register Address register NRZHTMM 04H DBF0, DBF1 PUT GET PUTNote 1 GETNote 2 Peripheral Register Transferring Data with Data Buffer Symbol TMC TMM Peripheral address Data buffer used 05H 06H DBF0, DBF1 DBF0, DBF1 PUT/GET GET only PUT only NRZLTMM 03H DBF0, DBF1 PUT GET AR 40H DBF0 to DBF3 Notes 1. In the PD17240: Bits 0 to 3 of AR3 and bit 3 of AR2 are arbitrary values In the PD17241: Bits 0 to 3 of AR3 are arbitrary values In the PD17242, 17243: Bits 1 to 3 of AR3 are arbitrary values In the PD17244, 17245, 17246: Bits 2 to 3 of AR3 are arbitrary values 2. In the PD17240: Bits 0 to 3 of AR3 and bit 3 of AR2 are always 0 In the PD17241: Bits 0 to 3 of AR3 are always 0 In the PD17242, 17243: Bits 1 to 3 of AR3 are always 0 In the PD17244, 17245, 17246: Bits 2 to 3 of AR3 are always 0 (2) Table referencing An MOVT instruction reads constant data from a specified location of the program memory (ROM) and sets it in the data buffer. The function of the MOVT instruction is explained below. MOVT DBF, @AR: Reads data from a program memory location pointed to by the address register (AR) and sets it in the data buffer (DBF). Data buffer DBF 3 DBF 2 DBF 1 DBF 0 Program memory (ROM) MOVT DBF, @ AR 16 bits b15 b0 Data Sheet U15002EJ1V0DS 29 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 (3) Notes on using data buffer When transferring data to/from the peripheral hardware via the data buffer, the unused peripheral addresses, write-only peripheral registers (only when executing PUT), and read-only peripheral registers (only when executing GET) must be handled as follows. * When device operates Nothing changes even if data is written to a read-only register. If an unused address is read, an undefined value is read. Nothing changes even if data is written to that address. * Using assembler An error occurs if an instruction is executed to read a write-only register. Again, an error occurs if an instruction is executed to write data to a read-only register. An error also occurs if an instruction is executed to read or write an unused address. * If an in-circuit emulator (IE-17K or IE-17K-ET) is used (when an instruction is executed for patch processing) An undefined value is read if an attempt is made to read the data of a write-only register, but an error does not occur. Nothing changes even if data is written to a read-only register, and an error does not occur. An undefined value is read if an unused address is read; nothing changes even if data is written to this address. An error does not occur. 30 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 2.5 Register File (RF) The register file mainly consists of registers that set the conditions of the peripheral hardware. These registers can be controlled by the dedicated instructions PEEK and POKE, and the embedded macro instructions of RA17K, SETn, CLRn, and INITFLG. 2.5.1 Configuration of register file Figure 2-10 shows the configuration of the register file and how the register file is accessed by the PEEK and POKE instructions. The control registers are controlled by using dedicated instructions PEEK and POKE. Since the control registers are assigned to addresses 00H to 3FH regardless of the bank, the addresses 00H to 3FH of the general-purpose data memory cannot be accessed when the PEEK or POKE instruction is used. The addresses that can be accessed by the PEEK and POKE instructions are addresses 00H to 3FH of the control registers and 40H to 7FH of the general-purpose data memory. The register file consists of these addresses. The control registers are assigned to addresses 80H to BFH on the IE-17K to facilitate debugging. Figure 2-10. Register File Configuration and Register File Access with PEEK or POKE Instructions Column address 6 7 8 9 0 0 1 2 3 4 5 6 7 Row address 1 2 3 4 5 A B C D E F Data memory POKE M063, WR System register 0 1 2 POKE LCDMD, WR 3 Register file Control register PEEK WR, SP Data Sheet U15002EJ1V0DS 31 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 2.5.2 Control registers The control registers consist of a total of 64 nibbles (64 x 4 bits) of addresses 00H to 3FH of the register file. Of these, however, only 24 nibbles are actually used. The remaining 40 nibbles are unused registers that are prohibited from being read or written. When the "PEEK WR, rf" instruction is executed, the contents of the register file addressed by "rf" are read to the window register. When the "POKE rf, WR" instruction is executed, the contents of the window register are written to the register file addressed by "rf". When using the assembler (RA17K), the macro instructions listed below, which are embedded as flag type symbol manipulation instructions, can be used. The macro instructions allow the contents of the register file to be manipulated in bit units. For the configuration of the control register, refer to Figure 12-1 Register File List. SETn: CLRn: SKTn: SKFn: NOTn: INITFLG: Sets flag to "1" Sets flag to "0" Skips if all flags are "1" Skips if all flags are "0" Inverts flag Initializes flag INITFLGX: Initializes flag 2.5.3 Notes on using register files When using the register files, bear in mind the points described below. For details, refer to the PD172xx Subseries User's Manual (U12795E). (1) When manipulating control registers (read-only and unused registers) When manipulating the write-only (W), the read-only (R), and unused control registers by using an assembler or in-circuit emulator, keep in mind the following points. * When device operates Nothing changes even if data is written to a read-only register. If an unused register is read, an undefined value is read; nothing is changed even if data is written to this register. * Using assembler An error occurs if an instruction is executed to read data from a write-only register. An error occurs if an instruction is executed to write data to a read-only register. An error also occurs if an instruction is executed to read or write an unused address. * When an in-circuit emulator (IE-17K or IE-17K-ET) is used (when an instruction is executed for patch processing) An undefined value is read if a write-only register is read, and an error does not occur. Nothing changes even if data is written to a read-only register, and an error does not occur. An undefined value is read if an unused address is read; nothing changes even if data is written to this address. An error does not occur. 32 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 (2) Symbol definition of register file An error occurs if a register file address is directly specified as a numeral by the operand "rf" of the "PEEK WR, rf" or "POKE rf, WR" instruction if the 17K Series Assembler (RA17K) is being used. Therefore, the addresses of the register file must be defined in advance as symbols. To define the addresses of the control registers as symbols, define them as addresses 80H to BFH of BANK0. The portion of the register file overlapping the data memory (40H to 7FH), however, can be defined as symbols as is. Data Sheet U15002EJ1V0DS 33 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3. 3.1 PORTS Port 0A (P0A0 to P0A3) This is a 4-bit input port. Data is read using port register P0A (address 70H of BANK0). This port is a CMOS input port with a pull-up resistor, and can be used as the key return input lines of a key matrix. In the standby mode, the standby status is released when a low level is input to at least one of these pins. 3.2 Port 0B (P0B0 to P0B3) This is a 4-bit I/O port which can be set to the input or output mode in 1-bit units by using P0BBIO (address 26H) of the register file. In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input to at least one of these pins. In the output mode, these pins serve as N-ch open-drain output pins and can be used as the key source lines of a key matrix. The data input to this port can be read or the data output from this port can be set by using the P0B register (address 71H of BANK0). When this port is read in the output mode, the contents of the output latch are read. In the input mode, a pull-up resistor of 200 k is connected to each bit of this port. In the output mode, the pullup resistor is disconnected. After reset, this port is set to the input mode. 3.3 Port 0C (P0C0 to P0C3) This is a 4-bit I/O port which can be set to the input or output mode in 4-bit units (group I/O) by using P0CDGIO (bit 2 of address 37H) of the register file. In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input to at least one of these pins. In the output mode, these pins serve as N-ch open-drain output pins and can be used as the key source lines of a key matrix. The data input to this port can be read or the data output from this port can be set by using the P0C register (address 72H of BANK0). When this port is read in the output mode, the contents of the output latch are read. In the input mode, a pull-up resistor of 200 k is connected to each bit of this port. In the output mode, the pullup resistor is disconnected. After reset, this port is set to the output mode and outputs a low level. 3.4 Port 0D (P0D0 to P0D3) This is a 4-bit I/O port which can be set to the input or output mode in 4-bit units (group I/O) by using P0CDGIO (bit 3 of address 37H) of the register file. In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input to at least one of these pins. In the output mode, these pins serve as N-ch open-drain output pins and can be used as the key source lines of a key matrix. The data input to this port can be read or the data output from this port can be set by using the P0D register (address 73H of BANK0). When this port is read in the output mode, the contents of the output latch are read. In the input mode, a pull-up resistor of 200 k is connected to each bit of this port. In the output mode, the pullup resistor is disconnected. After reset, this port is set to the output mode and outputs a low level. 34 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3.5 Port 0E (P0E0 to P0E3) This is a 4-bit I/O port. The input mode or output mode and whether a key matrix is used or not can be set for this port in 1-bit units. The input and output modes of this port are selected by using P0EBIO (address 27H) of the register file. Whether a key matrix is used or not is specified by P0EKEY (address 16H) of the register file. If this port is set to the input mode when a key matrix is used, it functions as a CMOS input port with a pull-up resistor and can be used to input key return signals. If one of the pins of this port goes low, the standby mode is released. If this port is set to the output mode when a key matrix is used, it functions as an N-ch open-drain output port and can be used to output key matrix signals. If this port is set to the input mode when a key matrix is not used, it functions as a CMOS input port to/from which a pull-up resistor can be connected/disconnected in 1-bit units, by using P0EBPU (address 17H) of the register file (if a pull-up resistor is connected, it is not disconnected even if the output mode is set). At this time, the standby mode is not released. If this port is set to the output mode when a key matrix is not used, it functions as a high-current CMOS output port. To read the input data from this port or set output data to it, use the P0E register (address 6FH of BANK0). When this port is read in the output mode, the contents of the output latch are read. After reset, this port is set to the input mode (a key matrix is not used and a resistor is not connected). 3.6 Port 1A (P1A0 to P1A2) These pins constitute a 3-bit I/O port that can be set in the input or output mode in 1-bit units. If this port is set to the input mode when a key matrix is used, it functions as a CMOS input port and can be used to input key return signals. At this time, whether a resistor is connected to this port and the standby mode release condition (whether it is released when this port is high or low) can be selected. 1. If connection of a resistor is specified and if it is specified that the standby mode is released when this port goes low ... A pull-up resistor is connected. If a low level is input to the set key, the standby mode is released. 2. If connection of a resistor is specified and if it is specified that the standby mode is released when this port goes high ... A pull-down resistor is connected. If a high level is input to the set key, the standby mode is released. 3. If connection of a resistor is not specified and if it is specified that the standby mode is released when this port goes low (or high) ... No resistor is connected. If a low (or high) level is input to the set key, the standby mode is released. If this port is set to the output mode when a key matrix is used, it functions as an N-ch open-drain output port and can be used to output key matrix signals. If this port is set to the input mode when a key matrix is not used, it functions as a CMOS input port. Connection of a resistor to this port and whether a pull-up or pull-down resistor is connected to the port can be selected in 1-bit units. At this time, the standby mode is not released. If this port is set to the output mode when a key matrix is not used, it functions as a high-current CMOS output port. To set this port to the input mode or output mode, use P1ABIO (address 25H) of the register file. To specify whether a key matrix is used or not, use P1AKEY (address 06H) of the register file. To specify whether a resistor is connected, use P1ABPU (address 07H) of the register file. To specify the standby mode release condition (to specify whether a pull-down or pull-up resistor is connected when a key matrix is not used), use P1AHL (address 05H) of the register file. Use the P1A register (address 70H of BANK1) to read the input data from this port or set output data to it. When this port is read in the output mode, the contents of the output latch are read. After reset, this port is set to the input mode (a key matrix is not used and a resistor is not connected). Data Sheet U15002EJ1V0DS 35 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3.7 Port 1B (P1B0) The P1B0 pin functions alternately as the INT pin. To use the P1B0 pin, set INTSEL (bit 1 of address 1FH) of the register file to 0. The P1B0 pin functions as a 1-bit CMOS input port. This port can be used to input a key return signal when a key matrix is used. At this time, whether a resistor is connected to this port and the standby mode release condition (whether it is released when this pin is high or low) can be selected. 1. If connection of a resistor is specified and if it is specified that the standby mode is released when this pin goes low ... A pull-up resistor is connected. If a low level is input to P1B0, the standby mode is released. 2. If connection of a resistor is specified and if it is specified that the standby mode is released when this pin goes high ... A pull-down resistor is connected. If a high level is input to P1B0, the standby mode is released. 3. If connection of a resistor is not specified and if it is specified that the standby mode is released when this pin goes low (or high) ... No resistor is connected. If a low (or high) level is input to P1B0, the standby mode is released. If a key matrix is not used, whether a resistor is connected and whether a pull-up or pull-down resistor is connected can be selected. At this time, the standby mode is not released. To specify whether a resistor is connected, use P1BPU0 (bit 0 of address 05H) of the register file. To specify whether a key matrix is used or not, use P1BKEY0 (bit 1 of address 05H) of the register file. To specify a standby condition (to specify whether a pull-down or pull-up resistor is connected when a key matrix is not used), use P1BHL0 (bit 2 of address 05H) of the register file. Use the P1B register (address 71H of BANK1) to read the input data. After reset, the P1B0 pin is selected and functions as an input port (a key matrix is not used and a resistor is not connected). 36 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3.8 INT Pin The INT pin functions alternately as the P1B0 pin. To use the INT pin, set INTSEL (bit 1 of address 1FH) of the register file to 1. This pin inputs an external interrupt request signal. The IRQ flag (RF: bit 0 of address 3EH) is set at either the rising or falling edge of the signal input to this pin. The status of this pin can be read by using the INT flag (RF: bit 0 of address 0FH). When a high level is input to the pin, the INT flag is set to "1"; when a low level is input, the flag is reset to "0" (refer to 8.2.1 INT). Table 3-1. Relationship Between Port Register and Each Pin Bank Address Target Port Bit Output Format 0 70H Port 0A b3 b2 b1 b0 71H Port 0B b3 b2 b1 b0 72H Port 0C b3 b2 b1 b0 73H Port 0D b3 b2 b1 b0 6FH Port 0E b3 b2 b1 b0 P0A3 P0A2 P0A1 P0A0 P0B3 P0B2 P0B1 P0B0 P0C3 P0C2 P0C1 P0C0 P0D3 P0D2 P0D1 P0D0 P0E3 P0E2 P0E1 P0E0 CMOS push-pull or N-ch open drain Input mode (when key matrix not used and no pull-up resistor connected) Input mode (when key matrix not used and no resistor connected) - - - Input mode (when key matrix not used and no resistor connected) Output mode (low-level output) N-ch open drain Output latch Output latch Output latch Input Read Contents Written Contents After Reset Input mode Output mode Input mode Output mode Pin status - - - Input mode (with pull-up resistor) 1 70H Port 1A b2 b1 b0 P1A2 P1A1 P1A0 CMOS push-pull or N-ch open drain 71H Port 1B b0 P1B0 Input Data Sheet U15002EJ1V0DS 37 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3.9 Switching Bit I/O (Port 0B, 0E, 1A) An I/O that can be set to the input or output mode in bit units is called a bit I/O. P0B, P0E, and P1A are bit I/O ports, which can be set in the input or output mode in bit units by the register file shown below. When the mode is changed from input to output, the P0B, P0E, and P1A output latch contents are output to the port lines as soon as the mode has been changed. 3 P0BBIO3 2 P0BBIO2 1 P0BBIO1 0 P0BBIO0 Address RF: 26H After reset 0H R/W R/W P0BBIO0 0 1 Sets P0B0 input/output mode Sets P0B0 in input mode Sets P0B0 in output mode P0BBIO1 0 1 Sets P0B1 input/output mode Sets P0B1 in input mode Sets P0B1 in output mode P0BBIO2 0 1 Sets P0B2 input/output mode Sets P0B2 in input mode Sets P0B2 in output mode P0BBIO3 0 1 Sets P0B3 input/output mode Sets P0B3 in input mode Sets P0B3 in output mode 38 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3 P0EBIO3 2 P0EBIO2 1 P0EBIO1 0 P0EBIO0 Address RF: 27H After reset 0H R/W R/W P0EBIO0 0 1 Sets P0E0 input/output mode Sets P0E0 in input mode Sets P0E0 in output mode P0EBIO1 0 1 Sets P0E1 input/output mode Sets P0E1 in input mode Sets P0E1 in output mode P0EBIO2 0 1 Sets P0E2 input/output mode Sets P0E2 in input mode Sets P0E2 in output mode P0EBIO3 0 1 Sets P0E3 input/output mode Sets P0E3 in input mode Sets P0E3 in output mode 3 0 2 P1ABIO2 1 P1ABIO1 0 P1ABIO0 Address RF: 25H After reset 0H R/W R/W P1ABIO0 0 1 Sets P1A0 input/output mode Sets P1A0 in input mode Sets P1A0 in output mode P1ABIO1 0 1 Sets P1A1 input/output mode Sets P1A1 in input mode Sets P1A1 in output mode P1ABIO2 0 1 Sets P1A2 input/output mode Sets P1A2 in input mode Sets P1A2 in output mode Data Sheet U15002EJ1V0DS 39 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3.10 Selecting I/O Mode of Group I/O (Port 0C, 0D) An I/O that is set to the input or output mode in 4-bit units is called a group I/O. P0C and P0D can be used as group I/O ports. The input and output modes of these ports are selected by using the following register file. If the mode is changed from input to output, the contents of the port register are output to the respective ports as soon as the mode has been changed. 3 P0DGIO 2 P0CGIO 1 0 0 0 Address RF: 37H After reset CH R/W R/W P0CGIO 0 1 I/O mode of P0C0 to P0C3 Sets P0C0 to P0C3 in input mode Sets P0C0 to P0C3 in output mode P0DGIO 0 1 I/O mode of P0D0 to P0D3 Sets P0D0 to P0D3 in input mode Sets P0D0 to P0D3 in output mode 40 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3.11 Selecting Whether Key Matrix Is Used or Not (Port 0E, 1A) By using the following register file, whether P0E and P1A are used for a key matrix can be selected in bit units. 3 0 2 1 0 Address RF: 06H After reset 0H R/W R/W P1AKEY2 P1AKEY1 P1AKEY0 P1AKEY0 0 1 Selects whether P1A0 is used for key matrix or not P1A0 not used for key matrix P1A0 used for key matrix P1AKEY1 0 1 Selects whether P1A1 is used for key matrix or not P1A1 not used for key matrix P1A1 used for key matrix P1AKEY2 0 1 Selects whether P1A2 is used for key matrix or not P1A2 not used for key matrix P1A2 used for key matrix 3 2 1 0 Address RF: 16H After reset 0H R/W R/W P0EKEY3 P0EKEY2 P0EKEY1 P0EKEY0 P0EKEY0 0 1 Selects whether P0E0 is used for key matrix or not P0E0 not used for key matrix P0E0 used for key matrix P0EKEY1 0 1 Selects whether P0E1 is used for key matrix or not P0E1 not used for key matrix P0E1 used for key matrix P0EKEY2 0 1 Selects whether P0E2 is used for key matrix or not P0E2 not used for key matrix P0E2 used for key matrix P0EKEY3 0 1 Selects whether P0E3 is used for key matrix or not P0E3 not used for key matrix P0E3 used for key matrix Data Sheet U15002EJ1V0DS 41 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3.12 Specifying Resistor Connection (Port 0E, 1A) (1) Port 0E If a key matrix is not used, whether or not a pull-up resistor is connected to port P0E can be specified in 1bit units by using the following registers of the register fileNote. 3 2 1 0 Address RF: 17H After reset 0H R/W R/W P0EBPU3 P0EBPU2 P0EBPU1 P0EBPU0 P0EBPU0 0 1 Connects pull-up resistor to P0E0 Not connected Connected P0EBPU1 0 1 Connects pull-up resistor to P0E1 Not connected Connected P0EBPU2 0 1 Connects pull-up resistor to P0E2 Not connected Connected P0EBPU3 0 1 Connects pull-up resistor to P0E3 Not connected Connected Note To disconnect the pull-up resistor in the output mode, clear the corresponding bit of the P0EBPU register. 42 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 (2) Port 1A Whether a resistor is connected to each bit of port P1A when a key matrix is not used can be specified in 1bit units by using the following register fileNote. To connect a resistor, select whether a pull-down or pull-up resistor is to be connected, by using P1AHL (address 05H) of the register file. 3 0 2 1 0 Address RF: 07H After reset 0H R/W R/W P1ABPU2 P1ABPU1 P1ABPU0 P1ABPU0 0 1 Not connected Connected Connects resistor to P1A0 P1ABPU1 0 1 Not connected Connected Connects resistor to P1A1 P1ABPU2 0 1 Not connected Connected Connects resistor to P1A2 Note To disconnect the resistor in the output mode, clear the corresponding bit of the P1ABPU register. Data Sheet U15002EJ1V0DS 43 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3.13 Selecting Standby Mode Release Condition and Whether Pull-Up or Pull-Down Resistor Is Connected (Port 1A) The standby mode release condition and whether a pull-up or pull-down resistorNote is connected to P1A can be specified in 1-bit units by using the following register file. Note Specify whether a resistor is connected or not by using P1ABPU (address 07H) of the register file. (1) When key matrix is used (P1AKEYn = 1) 3 0 2 P1AHL2 1 P1AHL1 0 P1AHL0 Address RF: 05H After reset 0H R/W R/W P1AHL0 Connects pull-down/pull-up resistor to P1A0 and selects standby mode release condition Resistor is connected (P1ABPU0 = 1) Resistor is not connected (P1ABPU0 = 0) 0 Pull-up resistor No resistor Standby mode is released when a low level is input to P1A. 1 Pull-down resistor No resistor Standby mode is released when a high level is input to P1A. P1AHL1 Connects pull-down/pull-up resistor to P1A1 and selects standby mode release condition Resistor is connected (P1ABPU1 = 1) Resistor is not connected (P1ABPU1 = 0) 0 Pull-up resistor No resistor Standby mode is released when a low level is input to P1A. 1 Pull-down resistor No resistor Standby mode is released when a high level is input to P1A. P1AHL2 Connects pull-down/pull-up resistor to P1A2 and selects standby mode release condition Resistor is connected (P1ABPU2 = 1) Resistor is not connected (P1ABPU2 = 0) 0 Pull-up resistor No resistor Standby mode is released when a low level is input to P1A. 1 Pull-down resistor No resistor Standby mode is released when a high level is input to P1A. Remark P1AKEY: Address 06H of register file P1ABPU: Address 07H of register file n = 0 to 2 44 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 (2) When key matrix is not used (P1AKEYn = 0) 3 0 2 P1AHL2 1 P1AHL1 0 P1AHL0 Address RF: 05H After reset 0H R/W R/W P1AHL0 Connects pull-down/pull-up resistor to P1A0 Resistor is connected (P1ABPU0 = 1) Resistor is not connected (P1ABPU0 = 0) 0 1 Pull-up resistor Pull-down resistor No resistor P1AHL1 Connects pull-down/pull-up resistor to P1A1 Resistor is connected (P1ABPU1 = 1) Resistor is not connected (P1ABPU1 = 0) 0 1 Pull-up resistor Pull-down resistor No resistor P1AHL2 Connects pull-down/pull-up resistor to P1A2 Resistor is connected (P1ABPU2 = 1) Resistor is not connected (P1ABPU2 = 0) 0 1 Pull-up resistor Pull-down resistor No resistor Caution The standby mode is not released by P1A when a key matrix is not used. Remark P1AKEY: Address 06H of register file P1ABPU: Address 07H of register file n = 0 to 2 Data Sheet U15002EJ1V0DS 45 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3.14 Selecting Whether Key Matrix Is Used, Standby Mode Release Condition, and Whether Pull-Up or Pull-Down Resistor Is Connected (Port 1B) Whether a key matrix is used or not, whether a resistor is connected to P1B or not, whether a pull-up or pull-down resistor is connected, and the standby mode release condition can be specified by using the following register file. 3 0 2 P1BHL0 1 P1BKEY0 0 P1BPU0 Address RF: 15H After reset 0H R/W R/W P1BPU0 0 1 Not connected Connected Connects resistor to P1B0 P1BKEY0 0 1 Selects whether P1B0 is used for key matrix or not P1B0 not used for key matrix P1B0 used for key matrix * When key matrix is used (P1BKEY0 = 1) P1BHL0 Connects pull-down/pull-up resistor to P1B0 and selects standby mode release condition Resistor is connected (P1BPU0 = 1) Resistor is not connected (P1BPU0 = 0) 0 Pull-up resistor No resistor Standby mode is released when a low level is input to P1B. 1 Pull-down resistor No resistor Standby mode is released when a high level is input to P1B. * When key matrix is not used (P1BKEY0 = 0) P1BHL0 Connects pull-down/pull-up resistor to P1B0 Resistor is connected (P1BPU0 = 1) Resistor is not connected (P1BPU0 = 0) 0 1 Pull-up resistor Pull-down resistor No resistor Caution The standby mode is not released by P1B when a key matrix is not used. 46 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 4. 4.1 CLOCK GENERATOR Instruction Execution Time (CPU Clock) Selection The PD17246 is equipped with a clock oscillator that supplies clocks to the CPU and peripheral hardware. Instruction execution time can be changed in two steps (normal mode and high-speed mode) without changing the oscillation frequency. To change the instruction execution time, change the mode of SYSCK (RF: address 02H) of the register file by using the POKE instruction. Note, that the mode is actually only changed when the instruction next to the POKE instruction has been executed. When using the high-speed mode, pay attention to the supply voltage. (Refer to 14. ELECTRICAL SPECIFICATIONS.) After reset, the normal mode is set. 3 0 2 0 1 0 0 SYSCK Address RF: 02H After reset 0H R/W R/W SYSCK 0 1 Selects instruction execution time Normal mode 32/fX (8 s) High-speed mode 16/fX (4 s) Values in parentheses apply to operation when the system clock fX = 4 MHz. Data Sheet U15002EJ1V0DS 47 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 5. 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR The PD17246 is equipped with an 8-bit timer, which is mainly used to generate the leader pulse of the remote controller signal and to output codes. 5.1 Configuration of 8-Bit Timer (with Modulo Function) Figure 5-1 shows the configuration of the 8-bit timer. As shown in this figure, the 8-bit timer consists of an 8-bit counter (TMC), an 8-bit modulo register (TMM), a comparator that compares the value of the timer with the value of the modulo register, and a selector that selects the operation clock of the 8-bit timer. To start/stop the 8-bit timer, and to reset the 8-bit counter, TMEN (address 33H, bit 3) and TMRES (address 33H, bit 2) of the register file are used. To select the operation clock of the 8-bit timer, use TMCK1 (address 33H, bit 1) and TMCK0 (address 33H, bit 0) of the register file. The value of the 8-bit counter is read by using the GET instruction through the DBF (data buffer). No value can be set to the 8-bit counter. A value is set to the modulo register by using the PUT instruction through DBF. The value of the modulo register cannot be read. When the value of the counter matches with that of the modulo register, an interrupt flag (IRQTM: address 3FH, bit 0) of the register file is set. TMC 7 6 5 4 3 2 1 0 Address Peripheral register: 05H After reset 00H R/W R 8-bit counter TMM 7 6 5 4 3 2 1 0 Address Peripheral register: 06H After reset FFH R/W W 8-bit modulo register Caution Do not clear TMM to 0 (IRQTM is not set). 48 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Figure 5-1. Configuration of 8-Bit Timer and Remote Controller Carrier Generator Data buffer Internal bus RF: 33H TMEN TMRES TMCK1 TMCK0 8-bit timer fX/32 Selector fX/64 fX/256 R S Q 8-bit modulo register TMM IRQTM Comparator 8-bit counter TMC Remote controller carrier generator fX/2 fX 2fX SW 8-bit counter RF: 11H Comparator NRZBF RF: 12H 8-bit modulo register NRZLTMM NRZ RF: 12H 8-bit counter REMEN Comparator REM 8-bit modulo register NRZHTMM Remark TMM, TMC, NRZLTMM, and NRZHTMM are peripheral registers. Data Sheet U15002EJ1V0DS 49 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 5.2 Function of 8-Bit Timer (with Modulo Function) 3 TMEN 2 TMRES 1 TMCK1 0 TMCK0 Address RF: 33H After reset 8HNote 1 R/W R/WNote 2 TMCK1 0 TMCK0 0 8-bit timer clock source selection Count clock: fX/32 (measurable time range: 8 s to 2.048 ms, resolution: 8 s (error: +8 s)) Count clock: fX/64 (measurable time range: 16 s to 4.096 ms, resolution: 16 s (error: +16 s)) Count clock: fX/256 (measurable time range: 64 s to 16.384 ms, resolution: 64 s (error: +64 s)) Remote controller carrier generator output 0 1 1 1 0 1 Values in parentheses apply to operation when system clock fX = 4 MHz. TMRES 0 1 8-bit timer reset flag Data read out is always "0" Resets 8-bit counter and IRQTM TMEN 0 1 8-bit timer count enable flag Stops 8-bit timer count operation Enables 8-bit timer count operation (falling edge) Notes 1. When the STOP mode is released, bit 3 must be set. 2. Bit 2 is a write-only bit. Caution If the system clock is changed while the timer is counting, an error occurs in the timer as follows (when system clock fX = 4 MHz): * High-speed mode 16/fX Normal mode 32/fX ... (Error due to resolution of set timer) +1.5 s * Normal mode 32/fX High-speed mode 16/fX ... (Error due to resolution of set timer) -1.5 s 50 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 5.3 Carrier Generator for Remote Controller PD17246 is provided with a carrier generator for the remote controller. The remote controller carrier generator consists of an 8-bit counter, NRZ high-level timer modulo register (NRZHTMM), and NRZ low-level timer modulo register (NRZLTMM). The high-level and low-level periods are set in the corresponding modulo registers through the DBF to determine the carrier duty factor and carrier frequency. As a clock input to the 8-bit counter, fX/2, fX, or 2fX can be selected by using REMCK0 and REMCK1 (address 13H, bits 0 and 1) of the register file (this clock for carrier generation is RfX). When RfX is oscillated by a 4 MHz resonator, therefore, the input clock is 2 MHz (fX/2), 4 MHz (fX), or 8 MHz (2fX). The NRZ high-level output timer modulo register is called NRZHTMM, and the NRZ low-level timer modulo register is called NRZLTMM. Data is written to these registers by the PUT instruction. The contents in these register are read by the GET instruction. Whether the REM pin outputs a carrier or a high level is selected by REMEN (address 12H, bit 1) of the register file. Be sure to clear this bit to 0 to output a carrier. NRZLTMM 7 6 5 4 3 2 1 0 Address Peripheral register: 03H After reset Undefined R/W R/W 8-bit modulo register NRZHTMM 7 6 5 4 3 2 1 0 Address Peripheral register: 03H After reset Undefined R/W R/W 8-bit modulo register 3 0 2 0 1 REMCK1 0 REMCK0 Address RF: 13H After reset 0H R/W R/W REMCK1 0 0 1 1 REMCK0 0 1 0 1 Clock for carrier generation (RfX) RfX = fX/2 (when fX = 4 MHz, RfX = 2 MHz) RfX = fX (when fX = 4 MHz, Rfx = 4 MHz) RfX = 2fXNote (when fX = 4 MHz, RfX = 8 MHz) Note RfX = 2fX can be selected only when fX = 3.5 to 4.5 MHz. Data Sheet U15002EJ1V0DS 51 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 5.3.1 Remote controller signal output control The REM pin, which outputs the carrier, is controlled by bits NRZ and NRZBF of the register file and timer 0. While the NRZ contents are "1", the clock generated by the remote controller carrier generator is output to the REM pin; while the NRZ contents are "0", the REM pin outputs a low level. The NRZBF contents are automatically transferred to NRZ by the interrupt signal generated by timer 0. If data is set in NRZBF in advance, the REM pin status changes in synchronization with the timer 0 counting operation. If the interrupt signal is generated from timer 0 with the REM pin at the high level (i.e. NRZ is "1") and the carrier clock at the high level, the REM pin output does not accord with the updated contents of NRZ until the carrier clock goes low. This processing is useful for holding the high level pulse width from the output carrier constant (refer to the figure below). When the contents of NRZ are "0", the remote controller carrier generator stops. However, if the clock for timer 0 is output from the remote controller carrier generator, the clock continues to operate, even when the NRZ contents become "0". An actual example showing a remote controller signal output to the REM pin is given below. When REMEN (address 12H, bit 1) of register file is 0 (carrier output) NRZ REM MAX. 500 ns (delay)Note (fX = 4 MHz, RfX = fX/2) REM pin does not go low until carrier goes low even if NRZ becomes 0 Note Value when (TMCK1, TMCK0) (1, 1). When (TMCK1, TMCK0) = (1, 1), the value differs depending on how NRZ is manipulated. If NRZ is set by an instruction, the width of the first high-level pulse may be shortened. If NRZ is set by data transferred from NRZBF, the high-level pulse is delayed by the low-level pulse of the carrier clock. 52 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 When REMEN (address 12H, bit 1) of register file is 1 (carrier not output) NRZ REM 3 0 2 0 1 REMEN 0 NRZ Address RF: 12H After reset 0H R/W R/W REMEN 0 0 1 1 NRZ 0 1 0 1 NRZ data Outputs low level to REM pin Outputs a carrier to REM pin Outputs low level to REM pin Outputs high level to REM pin 3 0 2 0 1 0 0 NRZBF Address RF: 11H After reset 0H R/W R/W NRZBF 0 1 NRZ data output next NRZ buffer bit. Transferred to NRZ by interrupt signal of timer 0. Data Sheet U15002EJ1V0DS 53 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Setting carrier frequency and duty factor Where the system clock frequency is fX, carrier frequency is fC, and carrier generation clock is RfX: * * * When RfX = fX/2: When RfX = fX: When RfX = 2fX: (division ratio) = fX/(2 x fC) (division ratio) = fX/fC (division ratio) = 2fX/fC is divided into m:n and is set in the modulo registers as follows: High-level period set value = { Low-level period set value = { Example x m/(m + n)} - 1 x n/(m + n)} - 1 Where fC = 38 kHz, duty factor (high-level period) = 1/3, fX = 4 MHz, and RfX = 2fX: = 2 x 4 MHz/38 kHz = 210.5 m:n = 1:2 From the above, the value of the modulo register is: High-level period . . 69 = .= 139 Low-level period . Therefore, the carrier frequency is 38.10 kHz. Table 5-1. Carrier Frequency List (1) Where fX = 4 MHz and RfX = fX/2 Set Value NRZHTMM 00H 01H 04H 09H 0FH 0FH 11H 11H 19H 3FH 7FH FFH NRZLTMM 00H 02H 04H 09H 10H 21H 21H 22H 35H 3FH 7FH FFH 0.5 1.0 2.5 5.0 8.0 8.0 9.0 9.0 13.0 32.0 64.0 128.0 0.5 1.5 2.5 5.0 8.5 17.0 17.0 17.5 27.0 32.0 64.0 128.0 1.0 2.5 5.0 10.0 16.5 25.0 26.0 26.5 40.0 64.0 128.0 256.0 1000 400 200 100 60.6 40.0 38.5 37.7 25.0 15.6 7.8 3.9 1/2 2/5 1/2 1/2 1/2 1/3 1/3 1/3 1/3 1/2 1/2 1/2 tH (s) tL (s) 1/fC (s) fC (kHz) Duty 54 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 (2) Where fX = 4 MHz, RfX = fX (original oscillation) Set Value NRZHTMM 00H 01H 04H 09H 0FH 0FH 11H 11H 19H 3FH 7FH FFH NRZLTMM 00H 02H 04H 09H 10H 21H 21H 22H 35H 3FH 7FH FFH 0.25 0.5 1.25 2.5 4.0 4.0 4.5 4.5 6.5 16.0 32.0 64.0 0.25 0.75 1.25 2.5 4.25 8.5 8.5 8.75 13.5 16.0 32.0 64.0 0.5 1.25 2.5 5.0 8.25 12.5 13.0 13.25 20.0 32.0 64.0 128.0 2000 800 400 200 121 80 76.9 75.47 50 31.25 15.6 7.8 1/2 2/5 1/2 1/2 1/2 1/3 1/3 1/3 1/3 1/2 1/2 1/2 tH (s) tL (s) 1/fC (s) fC (kHz) Duty (3) Where fX = 4 MHz, RfX = 2fX Set Value NRZHTMM 00H 07H 13H 27H 41H 41H 45H 45H 69H C7H FFH NRZLTMM 00H 0BH 13H 27H 41H 85H 89H 8BH D5H C7H FFH 0.125 1.0 2.5 5.0 8.25 8.25 8.75 8.75 13.25 25.0 32.0 0.125 1.5 2.5 5.0 8.25 16.75 17.25 17.5 26.75 25.0 32.0 0.25 2.5 5.0 10 16.5 25 26.0 26.25 40.0 50.0 64.0 4,000 400 200 100 60.6 40 38.5 38.10 25 20 15.6 1/2 2/5 1/2 1/2 1/2 1/3 1/3 1/3 1/3 1/2 1/2 tH (s) tL (s) 1/fC (s) fC (kHz) Duty tH tL REM (fC) 1/fC Data Sheet U15002EJ1V0DS 55 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 5.3.2 Countermeasures against noise during transmission (carrier output) When a signal is transmitted from the transmitter of a remote controller, a peak current of 0.5 to 1 A may flow through the infrared LED. Since two batteries are usually used as the power source of the transmitter, several of equivalent resistance (r) exists in the power source as shown in Figure 5-2. This resistance increases to 10 to 20 if the supply voltage drops to 2 V. While the carrier is being output from the REM pin (while the infrared LED lights), therefore, a high-frequency noise may be generated on the power lines due to the voltage fluctuation that may take place especially during switching. To minimize the influence on the microcontroller of this high-frequency noise, take the following measures. <1> Separate the power lines of the microcontroller from the power lines of the infrared LED with the terminals of the batteries at the center. Use thick power lines and keep the wiring short. <2> Locate the resonator as close as possible to the microcontroller and shield it with GND lines (as indicated by the shaded portion in the figure below). <3> Locate the capacitor for stabilization of the power supply closely to the power lines of the microcontroller. Also, use a capacitor to eliminate high-frequency noise. <4> To prevent data from changing, do not execute data read/write processing such as key scan, an interrupt that requires a stack, or the CALL/RET instruction, while the carrier is being output. <5> To improve the reliability in case of program hang-up, use the watchdog timer. Figure 5-2. Example of Countermeasures Against Noise 0.5 to 1 A Infrared LED REM VDD Microcontroller r + - Batteries VSS 56 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 6. BASIC INTERVAL TIMER/WATCHDOG TIMER The basic interval timer has a function to generate the interval timer interrupt signal and watchdog timer reset signal. 6.1 Source Clock for Basic Interval Timer The system clock (fX) is divided to generate the source clock for the basic interval timer. The input clock frequency for the basic interval timer is fX/27. When the CPU is set in the STOP mode, the basic interval timer also stops. 6.2 Controlling Basic Interval Timer The basic interval timer is controlled by the bits in the register file. That is, the basic interval timer is reset by BTMRES. The frequency for the interrupt signal, output by the basic interval timer, is selected by BTMMD, and the watchdog timer is reset by WDTRES. Figure 6-1. Basic Interval Timer Configuration fX/218 fX/220 System clock fX 1/2 7 divider 1/2 11 divider 1/2 divider 1/2 divider 1/2 divider Selector B Reset signal output BTMRES WDTRES BTMCK IRQBTM Data Sheet U15002EJ1V0DS 57 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3 WDTRES 2 BTMCK 1 BTMRES 0 0 Address RF: 03H After reset 0H R/W R/WNote BTMRES 0 1 Basic interval timer reset Data read out is always "0" Writing "1" resets basic interval timer BTMCK 0 1 Basic interval timer mode selection Generates interrupt signal IRQBTM every fX/220 Generates interrupt signal IRQBTM every fX/218 WDTRES 0 1 Watchdog timer reset Data read out is always "0" Writing "1" resets watchdog timer (fX/221 counter) Note Bits 1 and 3 are write-only bits. 58 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 6.3 Operation Timing for Watchdog Timer The basic interval timer can be used as a watchdog timer. Unless the watchdog timer is reset within a fixed timeNote, it is judged that "the program has hung up", and the PD17246 is reset. It is therefore necessary to reset the watchdog timer via programming within the fixed time. The watchdog timer can be reset by setting WDTRES to 1. Note Fixed time: Approx. 340 ms (at 4 MHz) Caution The watchdog timer cannot be reset in the shaded range in Figure 6-2. Therefore, set WDTRES before both the fX/221 and fX/220 signals go high. Figure 6-2. Watchdog Timer Operation Timing fX/218 fX/219 fX/220 fX/221 INTBTM (fX/220) INTBTM (fX/218) Reset signal Watchdog timer reset signal Reset signal goes low if WDTRES is not set WDTRES Setting WDTRES at this timing is invalid Data Sheet U15002EJ1V0DS 59 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 7. 7.1 RAM RETENTION DETECTOR RAM Retention Flag The RAM retention flag (bit 0 of the register file at address 21H) indicates whether the supply voltage has dropped below the level at which the contents of the RAM are lost while the battery is being exchanged or when the battery voltage has dropped. This flag is at bit 3 of control register 0 (P3). It is cleared to 0 if the supply voltage drops below the RAM retention detection voltage (approx. 1.4 V TYP.). If this flag is 0, it can be judged that the RAM contents have been lost or that power has just been applied. This flag can be used to initialize the RAM via software. After initializing the RAM and writing the necessary data to it, set this RAM retention flag to "1" by software. At this time, 1 means that data has been set to the RAM. Figure 7-1. Supply Voltage Transition and Detection Voltage VDD VPOC (A) VID (B) POC detection voltage VPOC = 1.85 V (TYP.) RAM retention detection voltage VID = 1.4 V (TYP.) 0V (1) RAM retention flag (2) (3) (4) (5) (6) t Set to 1 Flag content is read. Flag content is read. (1) If the supply voltage rises after the battery has been set, and exceeds VPOC (POC detection voltage), reset is cleared. Because the supply voltage rises from 0 V, which is lower than VID (RAM retention detection voltage), the RAM retention flag remains in the initial status 0. (2) The supply voltage has now risen to the level at which the device can operate. Write the necessary data to the RAM and set the RAM retention flag to 1. (3) The device is reset if the supply voltage drops below VPOC. At point (A) in the above figure, the RAM retention flag remains 1 because the supply voltage is higher than VID at this point. (4) If the RAM retention flag is checked by software after reset has been cleared, it is 1. This means that the contents of the RAM have not been lost. It is therefore not necessary to initialize the RAM by software. (5) The device is reset if the supply voltage drops below VPOC. At point (B) in the figure, the voltage is lower than VID. Consequently, the RAM retention flag is cleared to 0. (6) If the RAM retention flag is checked by software after reset has been cleared, it is 0. This means that the contents of the RAM may have been lost. If this happens, initialize the RAM by software. 60 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 3 0 2 0 1 0 0 RAMFLAG Address RF: 21H After reset Undefined Note R/W R/W RAMFLAG 0 1 RAM retention flag RAM data may be undefined. RAM data are retained. Note RAMFLAG is "0" when VDD is about 1.4 V or less, and "undefined" when VDD is about 1.4 V or more. Data Sheet U15002EJ1V0DS 61 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 8. 8.1 INTERRUPT FUNCTIONS Interrupt Sources PD17246 is provided with three interrupt sources. When an interrupt has been acknowledged, the program execution automatically branches to a predetermined address, which is called a vector address. A vector address is assigned to each interrupt source, as shown in Table 8-1. Table 8-1. Vector Address Priority 1 2 3 8-bit timer Interrupt Source Ext/Int Internal External Internal Vector Address 0004H 0003H 0002H INT pin rising and falling edges Basic interval timer Remark 0001H is normal address When more than one interrupt request is issued at the same time, the interrupts are acknowledged in sequence, starting from the one with the highest priority. Whether an interrupt is enabled or disabled is specified by the EI or DI instruction. The basic condition under which an interrupt is acknowledged is that the interrupt is enabled by the EI instruction. While the DI instruction is executed, or while an interrupt is acknowledged, the interrupt is disabled. To enable acknowledgement of an interrupt after the interrupt has been processed, the EI instruction must be executed before the RETI instruction. Acknowledging the interrupt is enabled by the EI instruction after the instruction next to the EI instruction has been executed. Therefore, no interrupt can be acknowledged between the EI and RETI instructions. Caution In interrupt processing, only the BCD, CMP, CY, Z, IXE flags are automatically saved to the stack by the hardware, to a maximum of three levels. Also, within the interrupt processing contents, when peripheral hardware (timer, A/D converter, etc. ) is accessed, the DBF and WR contents are not saved by the hardware. Accordingly, it is recommended that at the beginning of interrupt processing, DBF and WR be saved by software to RAM, and immediately before finishing interrupt processing, the saved contents be returned to their original location. 62 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 8.2 Hardware of Interrupt Controller This section describes the flags of the interrupt controller. (1) Interrupt request flag and interrupt enable flag The interrupt request flag (IRQxxx) is set to 1 when an interrupt request is generated, and is automatically cleared to 0 when the interrupt processing is executed. An interrupt enable flag (IPxxx) is provided for each interrupt request flag. When the IPxxx flag is 1, the interrupt is enabled; when it is 0, the interrupt is disabled. (2) EI/DI instruction Whether an acknowledged interrupt is executed or not is specified by the EI or DI instruction. When the EI instruction is executed, INTE (interrupt enable flag), which enables the interrupt, is set to 1. The INTE flag is not registered on the register file. Consequently, the status of this flag cannot be checked by an instruction. The DI flag clears the INTE flag to 0 to disable all the interrupts. The INTE flag is also cleared to 0 at reset, disabling all the interrupts. Table 8-2. Interrupt Request Flags and Interrupt Enable Flag Interrupt Request Flag IRQTM IRQ IRQBTM Signal Setting Interrupt Request Flag Interrupt Enable Flag IPTM IP IPBTM Reset by 8-bit timer. Set when edge of INT pin input signal is detected Reset by basic interval timer. 8.2.1 INT This flag reads the INT pin status. When a high level is input to the INT pin, this flag is set to 1; when a low level is input, the flag is reset to 0. 3 0 2 0 1 0 0 INT Address RF: 0FH After reset Undefined R/W R INT 0 1 INT pin level detection INT pin: Low level INT pin: High level Data Sheet U15002EJ1V0DS 63 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 8.2.2 IEG This pin selects the interrupt edge to be detected on the INT pin. When this flag is 0, the interrupt is detected at the rising edge; when it is 1, the interrupt is detected at the falling edge. 8.2.3 INTSEL This flag selects whether pin 3 is used as the INT pin or P1B0 pin. When INTSEL is cleared to 0, pin 3 functions as the P1B0 pin; when it is set to 1, the pin functions as the INT pin. After reset, the P1B0 pin is selected. 3 0 2 0 1 INTSEL 0 IEG Address RF: 1FH After reset 0H R/W R/W IEG 0 1 INT pin interrupt detection edge selection Rising edge of INT pin Falling edge of INT pin INTSEL 0 1 As P1B0 pin As INT pin Selection of pin 3 function 8.2.4 Interrupt enable flag This flag enables each interrupt source. When this flag is 1, the corresponding interrupt is enabled; when it is 0, the interrupt is disabled. 3 0 2 IPBTM 1 IP 0 IPTM Address RF: 2FH After reset 0H R/W R/W IPTM 0 1 8-bit timer interrupt enable flag Disables interrupt acknowledgement by 8-bit timer Enables interrupt acknowledgement by 8-bit timer IP 0 1 INT pin interrupt enable flag Disables interrupt acknowledgement by INT pin input Enables interrupt acknowledgement by INT pin input IPBTM 0 1 Basic interval timer interrupt enable flag Disables interrupt acknowledgement by basic interval timer Enables interrupt acknowledgement by basic interval timer 64 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 8.2.5 IRQ This is an interrupt request flag that indicates the interrupt request status. When an interrupt request is generated, this flag is set to 1. When the interrupt has been acknowledged, the interrupt request flag is reset to 0. The interrupt request flag can be read or written by the program. Therefore, when it is set to 1, an interrupt can be generated by the software. By writing 0 to the flag, the interrupt pending status can be canceled. 3 0 2 0 1 0 0 IRQBTM Address RF: 3DH After reset 0H R/W R/W IRQBTM 0 1 Basic interval timer interrupt request flag Interrupt request has not been made. Basic interval timer interrupt request has been made. 3 0 2 0 1 0 0 IRQ Address RF: 3EH After reset 0H R/W R/W IRQ 0 1 INT pin interrupt request flag Interrupt request has not been made. Interrupt request has been made at rising edge or falling edge of INT input. 3 0 2 0 1 0 0 IRQTM Address RF: 3FH After reset 1H Note R/W R/W IRQTM 0 1 8-bit timer interrupt request flag Interrupt request has not been made. 8-bit timer interrupt request has been made. Note It is also set to 1H after the STOP mode is released. Data Sheet U15002EJ1V0DS 65 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 8.3 Interrupt Sequence If the IRQxx flag is set to 1 when the IPxx flag is "1", interrupt processing is started after the instruction cycle of the instruction executed when the IRQxx flag was set has ended. Since the MOVT instruction, EI instruction, and the instruction that matches the condition to skip use two instruction cycles, the interrupt enabled while this instruction is executed is processed after the second instruction cycle is over. If the IPxx flag is "0", the interrupt processing is not performed even if the IRQxx flag is set, until the IPxx flag is set. If two or more interrupts are enabled simultaneously, the interrupts are processed starting from the one with the highest priority. The interrupt with the lower priority is held pending until the processing of the interrupt with the higher priority is finished. 8.3.1 Operations when interrupt is acknowledged When an interrupt has been acknowledged, the CPU performs processing in the following sequence: Clears IRQxxx corresponding to INTE flag and acknowledged interrupt Decrements value of stack pointer by 1 (SP - 1) Saves contents of program counter to stack addressed by stack pointer Loads vector address to program counter Save contents of PSWORD to interrupt stack register One instruction cycle is required to perform the above processing. 66 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 8.3.2 Returning from interrupt processing routine To return from an interrupt processing routine, use the RETI instruction. The following processing is then executed within an instruction cycle. Loads contents of stack addressed by stack pointer to program counter Loads contents of interrupt stack register to PSWORD Increments value of stack pointer by 1 To enable an interrupt after the processing of an interrupt has finished, the EI instruction must be executed immediately before the RETI instruction. Interrupt acknowledgement is enabled by the EI instruction after the instruction next to the EI instruction has been executed. Therefore, the interrupt is not acknowledged between the EI and RETI instructions. Data Sheet U15002EJ1V0DS 67 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 9. STANDBY FUNCTIONS The PD17246 is provided with HALT and STOP modes as standby functions. By using the standby function, current consumption can be reduced. In the HALT mode, the program is not executed, but the system clock fX is not stopped. This mode is maintained, until the HALT mode release condition is satisfied. In the STOP mode, the system clock is stopped and program execution is stopped. This mode is maintained, until the STOP mode release condition is satisfied. The HALT mode is set, when the HALT instruction has been executed. The STOP mode is set, when the STOP instruction has been executed. 9.1 HALT Mode In this mode, program execution is temporarily stopped, with the main clock continuing oscillation, to reduce current consumption. Use the HALT instruction to set the HALT mode. The HALT mode release condition can be specified by the operand for the HALT instruction, as shown in Table 9-1. After the HALT mode has been released, the operation is performed as shown in Table 9-2 and Figure 9-1. Caution Do not execute an instruction that clears the interrupt request flag (IRQxxx) for which the interrupt enable flag (IPxxx) is set immediately before the HALT 8H instruction; otherwise, the HALT mode may not be set. Table 9-1. HALT Mode Releasing Conditions Operand Value 0010B (02H) 1000B (08H) Release Conditions When interrupt request (IRQTM) occurs for 8-bit timer <1> When interrupt request (IRQTM, IRQBTM, or IRQ), whose interrupt enable flag (IPTM, IPBTM, or IP) is set, occurs <2> When any of P0A0 to P0A3 pins goes low <3> When P0B0 to P0B3, P0C0 to P0C3, and P0D0 to P0D3 are used as input pins and any of these goes low <4> If P0E0 to P0E3 are used as input pins when a key matrix is used and if any of these pins goes low <5> If P1A0 to P1A2 and P1B0 are used as input pins when a key matrix is used and if the level of any of these pins is the set clear levelNote Setting prohibited Other than above Note Set the clear level by using bits 0 to 2 (P1AHL0 to P1AHL2) of the register file at address 05H, and bit 2 (P1BHL0) at address 15H. 68 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Table 9-2. Operations After HALT Mode Release (a) HALT 08H HALT Mode Released by: When release condition of P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P0D0 to P0D3, P0E0 to P0E3, P1A0 to P1A2, P1B0 is satisfied When release condition is satisfied by interrupt request EI DI Disabled Enabled Disabled Enabled Standby mode is not released Instruction next to HALT is executed Standby mode is not released Branches to interrupt vector address Interrupt Status Don't care Interrupt Enable Flag Don't care Operations After HALT Mode Release Instruction next to HALT is executed (b) HALT 02H HALT Mode Released by: 8-bit timer Interrupt Status DI Interrupt Enable Flag Disabled Enabled EI Disabled Enabled Branches to interrupt vector address Operations After HALT Mode Release Instructions are executed from the instruction next to the HALT instruction. 9.2 HALT Instruction Execution Conditions The HALT instruction can be executed under special conditions, as shown in Table 9-3, to prevent the program from hanging up. If the conditions in Table 9-3 are not satisfied, the HALT instruction is treated as a NOP instruction. Table 9-3. HALT Instruction Execution Conditions Operand Value 0010B (02H) 1000B (08H) Execution Conditions When all interrupt request flags (IRQTM) of 8-bit timer are reset <1> When interrupt request flag (IRQTH, IRQBTM, or IRQ) is reset, corresponding to interrupt whose interrupt enable flag (IPTM, IPBTM, or IP) is set <2> When high level is input to all P0A0 to P0A3 pins <3> When P0B0 to P0B3, P0C0 to P0C3, and P0D0 to P0D3 are used as input pins, a high level must be input to all the pins. <4> A high level must be input to all the pins if P0E0 to P0E3 are used as input pins when a key matrix is used. <5> A level reverse to the set clear levelNote must be input to all the pins if P1A0 to P1A2 and P1B0 are used as input pins when a key matrix is used (for example, if the clear level is high, the execution condition is low-level input). Setting prohibited Other than above Note Set the clear level by using bits 0 to 2 (P1AHL0 to P1AHL2) of the register file at address 05H, and bit 2 (P1BHL0) at address 15H. Data Sheet U15002EJ1V0DS 69 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 9.3 STOP Mode In the STOP mode, the system clock (fX) oscillation is stopped and the program execution is stopped to minimize current consumption. To set the STOP mode, use the STOP instruction. The STOP mode release condition can be specified by the STOP instruction operand, as shown in Table 9-4. After the STOP mode has released, the PD17246 performs the following. <1> Resets IRQTM. <2> Starts the basic interval timer and watchdog timer (does not reset). <3> Resets and starts the 8-bit timer. <4> Executes the instruction next to [STOP 8H] when the current value of the 8-bit counter matches the value of the modulo register (IRQTM is set). The PD17246 oscillator is stopped when the STOP instruction has been executed (i.e., in the STOP mode). Oscillation is not resumed until the STOP mode is released. After the STOP mode has been released, the HALT mode is set. Set the time required to release the HALT mode by using the timer with modulo function. The time that elapses from when the STOP mode has been released by occurrence of an interrupt until an operation mode is set is shown in the following table. Caution Do not execute an instruction that clears the interrupt request flag (IRQxxx) for which the interrupt enable flag (IPxxx) is set immediately before the STOP 8H instruction; otherwise, the STOP mode may not be set. 8-Bit Modulo Register Set Value (TMM) Time Required to Set Operation Mode After STOP Mode Release At 4 MHz 40H FFH 4.160 ms (64 s x 65) 16.384 ms (64 s x 256) Caution To set the time required for an operation mode to be set after the STOP mode has been released, make sure that sufficient time is allowed for oscillation to stabilize. Remark Set the 8-bit modulo timer before executing STOP instruction. Table 9-4. STOP Mode Release Conditions Operand Value 1000B (08H) Release Conditions <1> When any of P0A0 to P0A3 pins goes low <2> When P0B0 to P0B3, P0C0 to P0C3, and P0D0 to P0D3 are used as input pins and any of these goes low <3> If the interrupt request (IRQ) of an interrupt for which the INT pin interrupt enable flag (IP) is set is generated at the rising or falling edge of the INT pin <4> If P0E0 to P0E3 are used as input pins when a key matrix is used and if any of these pins goes low <5> If P1A0 to P1A2 and P1B0 are used as input pins when a key matrix is used and if the level of any of these pins is the set clear levelNote Setting prohibited Other than above Note Set the clear level by using bits 0 to 2 (P1AHL0 to P1AHL2) of the register file at address 05H, and bit 2 (P1BHL0) at address 15H. 70 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 9.4 STOP Instruction Execution Conditions The STOP instruction can be executed under special conditions, as shown in Table 9-5, to prevent the program from hanging up. If the conditions in Table 9-5 are not satisfied, the STOP instruction is treated as an NOP instruction. Table 9-5. STOP Instruction Execution Conditions Operand Value 1000B (08H) Execution Conditions <1> High level input for all P0A0 to P0A3 pins <2> When P0B0 to P0B3, P0C0 to P0C3, and P0D0 to P0D3 are used as input pins and all pins are high <3> If the INT pin interrupt request flag (IRQ) for an interrupt for which the INT pin interrupt enable flag (IP) is set is reset <4> A high level must be input to all the pins if P0E0 to P0E3 are used as input pins when a key matrix is used. <5> A level reverse to the set clear levelNote must be input to all the pins if P1A0 to P1A2 and P1B0 are used as input pins when a key matrix is used (for example, if the clear level is high, the execution condition is low-level input). Setting prohibited Other than above Note Set the clear level by using bits 0 to 2 (P1AHL0 to P1AHL2) of the register file at address 05H, and bit 2 (P1BHL0) at address 15H. Data Sheet U15002EJ1V0DS 71 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 9.5 Releasing Standby Mode The operations for releasing the STOP and HALT modes are as shown in Figure 9-1. Figure 9-1. Operations After Standby Mode Release (a) Releasing STOP mode by interrupt Wait (time set by TMM) STOP instruction Standby release signal Operation mode Oscillation STOP mode Oscillation stops HALT mode Oscillation Operation mode Clock (b) Releasing HALT mode by interrupt HALT instruction Standby release signal Operation mode HALT mode Operation mode Clock Oscillation Remark The dotted line indicates the operation to be performed when the interrupt request releasing the standby mode has been acknowledged. 72 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 10. RESET 10.1 Reset by Reset Signal Input When a low-level signal of more than 10 s is input to the RESET pin, the PD17246 is reset. When the system is reset, the oscillator remains in the HALT mode and then enters an operation mode, in the same way as when the STOP mode is released. The wait time after the reset signal has been canceled is 16.384 ms (fX = 4 MHz). On power application, input the reset signal at least once because the internal circuitry operations are not stable. When PD17246 is reset, the following initialization takes place. (1) Program counter is reset to 0. (2) Flags in the register file are initialized to their default values (for the default values, refer to Figure 12-1 Register Files). (3) The default value (0320H) is written to the data buffer (DBF). (4) The hardware peripherals are initialized. (5) The system clock (fX) stops oscillation. When the RESET pin is made high, the system clock starts oscillating, and the program execution starts from address 0 about 16 ms (at 4 MHz) later. Figure 10-1. Reset Operation by RESET Input Wait (about 16 ms at 4 MHz) RESET Operation mode or standby mode Starts from address 0H HALT mode Operation mode Oscillation stops 10.2 Reset by Watchdog Timer (with RESET Pin Internally Pulled Down) When the watchdog timer operates during program execution, the RESET pin is internally pulled down, and the program counter is reset to 0 (normally, the RESET pin is pulled up). If the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0H. Program so that the watchdog timer is reset at intervals of within 340 ms (at fX = 4 MHz) (set the WDTRES flag). Data Sheet U15002EJ1V0DS 73 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 10.3 Reset by Stack Pointer (with RESET Pin Internally Pulled Down) When the value of the stack pointer reaches 6H or 7H during program execution, the RESET pin is internally pulled down, and the program counter is reset to 0 (normally, the RESET pin is pulled up). Therefore, if an interrupt or CALL instruction is executed when the value of the stack pointer is 0 (stack underflow) or if the stack level exceeds 6 as a result of execution of the RET instruction because the correspondence between the CALL and RET instructions is not established (stack overflow), the program can be restarted from address 0H. Table 10-1. Status of Each Hardware After Reset Hardware RESET Input in Standby Mode 0000H Input/output Output latch Data memory (RAM) General-purpose data memory (Except DBF, port register) DBF System register (SYSREG) WR Input 0 Retains previous status 0320H 0 Retains previous status RESET Input During Operation 0000H Input 0 Undefined Program counter (PC) Ports 0320H 0 Undefined Control registers 8-bit timer Counter (TMC) Modulo register (TMM) Remote controller carrier generator Refer to Figure 12-1 Register Files 00H FFH 00H FFH Undefined NRZ high-level timer modulo register (NRZHTMM) Retains previous NRZ low-level timer modulo register (NRZLTMM) status 00H Basic interval timer/watchdog timer counter 00H 74 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 11. LOW-VOLTAGE DETECTOR (WITH RESET PIN INTERNALLY PULLED DOWN) The RESET pin is internally pulled down for initialization (reset) to prevent program hang-up that may take place when the batteries are replaced, if the low-voltage detector detects a low voltage. A drop in the supply voltage is detected if the status in which VDD is about 1.7 to 2.0 V lasts for 1 ms or longer. Note, however, that 1 ms is the guaranteed value and that the microcontroller may be reset even if the above lowvoltage condition lasts for less than 1 ms. Although the voltage at which the reset function is effected ranges from about 1.7 to 2.0 V, the program counter is prevented from hanging up even if the supply voltage drops until the reset function is effected. Note that a resonator may stop oscillating before the reset function is effected if normal operation under the low voltage is not guaranteed. The low-voltage detector can be set arbitrarily by a mask option. Data Sheet U15002EJ1V0DS 75 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 12. ASSEMBLER RESERVED WORDS 12.1 Mask Option Directives When developing the PD17246 program, mask options must be specified by using mask option directives in the program. To select the low-voltage detector and capacitor for oscillation of the PD17246, a mask option must be specified. 12.1.1 OPTION and ENDOP directives The portion of the program enclosed by the OPTION and ENDOP directives is called a mask option definition block. This block is described in the following format. Description format: Symbol [Label: ] Mnemonic OPTION : : : ENDOP Operand Comment [;Comment] 12.1.2 Mask option definition directives Table 12-1 lists the directives that can be used in the mask option definition block. Here is an example of mask option definition. Description example: Symbol Mnemonic OPTION OPTPOC OPTCAP ENDOP USEPOC USECAP ; Internal low-voltage detector ; Internal capacitor for oscillation Operand Comment 76 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Table 12-1. Mask Option Definition Directives Name CAP Directive OPTCAP Operands 1 1st Operand USECAP (capacitor for oscillation provided) NOUSECAP (capacitor for oscillation not provided) POC OPTPOC 1 USEPOC (low-voltage detector provided) NOUSEPOC (low-voltage detector not provided) 2nd Operand 3rd Operand 4th Operand 12.2 Reserved Symbols The symbols defined by the PD17246 device file are listed in Table 12-2. The defined symbols are the following register file names, port names, and peripheral hardware names. 12.2.1 Register file The names of the symbols assigned to the register file are defined. These registers are accessed by the PEEK and POKE instructions via the window register (WR). Figure 12-1 shows the register file. 12.2.2 Registers and ports on data memory The names of the registers assigned to addresses 00H to 7FH on the data memory and the names of ports assigned to address 70H and those that follow, and system register names are defined. Figure 12-2 shows the data memory configuration. 12.2.3 Peripheral hardware The names of peripheral hardware accessed by the GET and PUT instructions are defined. Table 12-3 shows the peripheral hardware. Data Sheet U15002EJ1V0DS 77 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Table 12-2. Reserved Symbols (1/3) Symbol Name DBF3 DBF2 DBF1 DBF0 AR3 AR2 AR1 AR0 WR BANK IXH MPH MPE IXM MPL IXL RPH RPL PSW BCD CMP CY Z IXE P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 P0C0 P0C1 P0C2 P0C3 P0D0 P0D1 P0D2 P0D3 Attribute MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM FLG MEM MEM MEM MEM MEM MEM FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.0CH 0.0DH 0.0EH 0.0FH 0.74H 0.75H 0.76H 0.77H 0.78H 0.79H 0.7AH 0.7AH 0.7AH.3 0.7BH 0.7BH 0.7CH 0.7DH 0.7EH 0.7FH 0.7EH.0 0.7FH.3 0.7FH.2 0.7FH.1 0.7FH.0 0.70H.0 0.70H.1 0.70H.2 0.70H.3 0.71H.0 0.71H.1 0.71H.2 0.71H.3 0.72H.0 0.72H.1 0.72H.2 0.72H.3 0.73H.0 0.73H.1 0.73H.2 0.73H.3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bits 15 to 12 of data buffer Bits 11 to 8 of data buffer Bits 7 to 4 of data buffer Bits 3 to 0 of data buffer Bits 15 to 12 of address register Bits 11 to 8 of address register Bits 7 to 4 of address register Bits 3 to 0 of address register Window register Bank register Index register, high Data memory row address pointer, high Memory pointer enable flag Index register, middle Data memory row address pointer, low Index register, low General register pointer, high General register pointer, low Program status word BCD flag Compare flag Carry flag Zero flag Index enable flag Bit 0 of port 0A Bit 1 of port 0A Bit 2 of port 0A Bit 3 of port 0A Bit 0 of port 0B Bit 1 of port 0B Bit 2 of port 0B Bit 3 of port 0B Bit 0 of port 0C Bit 1 of port 0C Bit 2 of port 0C Bit 3 of port 0C Bit 0 of port 0D Bit 1 of port 0D Bit 2 of port 0D Bit 3 of port 0D 78 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Table 12-2. Reserved Symbols (2/3) Symbol Name P0E0 P0E1 P0E2 P0E3 P1A0 P1A1 P1A2 P1B0 SP SYSCK WDTRES BTMCK BTMRES P1AHL0 P1AHL1 P1AHL2 P1AKEY0 P1AKEY1 P1AKEY2 P1ABPU0 P1ABPU1 P1ABPU2 INT NRZBF NRZ REMEN REMCK1 REMCK0 P1BHL0 P1BKEY0 P1BBPU0 P0EKEY0 P0EKEY1 P0EKEY2 P0EKEY3 P0EBPU0 P0EBPU1 P0EBPU2 P0EBPU3 INTSEL Attribute FLG FLG FLG FLG FLG FLG FLG FLG MEM FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.6FH.0 0.6FH.1 0.6FH.2 0.6FH.3 1.70H.0 1.70H.1 1.70H.2 1.71H.0 0.81H 0.82H.0 0.83H.3 0.83H.2 0.83H.1 0.85H.0 0.85H.1 0.85H.2 0.86H.0 0.86H.1 0.86H.2 0.87H.0 0.87H.1 0.87H.2 0.8FH.0 0.91H.0 0.92H.0 0.92H.1 0.93H.1 0.93H.0 0.95H.2 0.95H.1 0.95H.0 0.96H.0 0.96H.1 0.96H.2 0.96H.3 0.97H.0 0.97H.1 0.97H.2 0.97H.3 0.9FH.1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 of port 0E Bit 1 of port 0E Bit 2 of port 0E Bit 3 of port 0E Bit 0 of port 1A Bit 1 of port 1A Bit 2 of port 1A Bit 0 of port 1B Stack pointer System clock select flag Watchdog timer reset flag Basic interval timer mode select flag Basic interval timer mode reset flag P1A0 port standby clear level select flag P1A1 port standby clear level select flag P1A2 port standby clear level select flag P1A0 port key matrix select flag P1A1 port key matrix select flag P1A2 port key matrix select flag P1A0 port pull-up resistor select flag P1A1 port pull-up resistor select flag P1A2 port pull-up resistor select flag INT pin status flag NRZ buffer data flag NRZ data flag Carrier output select flag Carrier generation clock select flag Carrier generation clock select flag P1B0 port standby clear level select flag P1B0 port key matrix select flag P1B0 port pull-up resistor select flag P1E0 port key matrix select flag P1E1 port key matrix select flag P1E2 port key matrix select flag P1E3 port key matrix select flag P0E0 pull-up setting flag P0E1 pull-up setting flag P0E2 pull-up setting flag P0E3 pull-up setting flag INT select flag Description Data Sheet U15002EJ1V0DS 79 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Table 12-2. Reserved Symbols (3/3) Symbol Name IEG RAMFLAG P1ABIO0 P1ABIO1 P1ABIO2 P0BBIO0 P0BBIO1 P0BBIO2 P0BBIO3 P0EBIO0 P0EBIO1 P0EBIO2 P0EBIO3 IPBTM IP IPTM TMEN TMRES TMCK1 TMCK0 P0CGIO P0DGIO IRQBTM IRQ IRQTM TMC TMM NRZLTMM NRZHTMM AR USECAP NOUSECAP USEPOC NOUSEPOC DBF IX AR_EPA1 Attribute FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT Value 0.9FH.0 0.0A1H.0 0.0A5H.0 0.0A5H.1 0.0A5H.2 0.0A6H.0 0.0A6H.1 0.0A6H.2 0.0A6H.3 0.0A7H.0 0.0A7H.1 0.0A7H.2 0.0A7H.3 0.0AFH.2 0.0AFH.1 0.0AFH.0 0.0B3H.3 0.0B3H.2 0.0B3H.1 0.0B3H.0 0.0B7H.2 0.0B7H.3 0.0BDH.0 0.0BEH.0 0.0BFH.0 05H 06H 03H 04H 40H 0FF11H 0FF22H 0FF33H 0FF44H 0FH 01H 8040H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W -- -- -- -- -- -- -- Description INT pin interrupt edge flag RAM retention flag P1A0 I/O select flag P1A1 I/O select flag P1A2 I/O select flag P0B0 I/O select flag P0B1 I/O select flag P0B2 I/O select flag P0B3 I/O select flag P0E0 I/O setting flag P0E1 I/O setting flag P0E2 I/O setting flag P0E3 I/O setting flag Basic interval timer interrupt enable flag INT pin interrupt enable flag Timer interrupt enable flag Timer enable flag Timer reset flag Timer clock flag Timer clock flag P0C3 to P0C0 I/O select flag P0D3 to P0D0 I/O select flag Basic interval timer interrupt request flag INT pin interrupt request flag Timer interrupt request flag Timer count register Timer modulo register NRZ low-level timer modulo register NRZ high-level timer modulo register Address register Capacitor with oscillator is used. Capacitor with oscillator is not used. POC circuit is used. POC circuit is not used. Fixed operand value for PUT, GET, MOVT instruction Fixed operand value for INC instruction Indicates that the EPA bit of AR is ON. 80 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Figure 12-1. Register Files (1/2) Column Address 0 1 2 3 4 5 6 7 Note Note Note Note Note Note Note Row Address Bit 3 0 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 1 Bit 1 Bit 0 Bit 3 Bit 2 2 Bit 1 Bit 0 Bit 3 Bit 2 3 Bit 1 Bit 0 0 1 SP 0 1 0 0 0 NRZBF 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCK 0 0 REMEN NRZ 0 WDTRES 0 0 BTMCK 0 0 P1AHL2 P1AHL1 P1AHL0 0 P1BHL0 0 0 0 0 0 0 P1AKEY2 0 P1ABPU2 0 0 P1AKEY1 0 P1ABPU1 0 0 P1AKEY0 0 P1ABPU0 0 0 P0EKEY3 0 P0EBPU3 0 0 P0EKEY2 0 P0EBPU2 0 0 BTMRES 0 0 0 0 0 0 0 0 0 0 0 REMCK1 0 0 REMCK0 0 P1BKEY0 0 P0EKEY1 0 P0EBPU1 0 P1BPU0 0 0 P0EKEY0 0 P0EBPU0 0 0 P0BBIO3 0 P0EBIO3 0 P0EBIO2 0 P0EBIO1 0 P0EBIO0 P0DGIO P0CGIO 0 0 0 0 0 0 1 1 0 0 P1ABIO2 0 P0BBIO2 P1ABIO1 0 P0BBIO1 P1ABIO0 0 P0BBIO0 TMEN TMRES TMCK1 TMCK0 1 0 0 0 RAMFLAG 0 Note After reset Figure 12-2. Data Memory Configuration Column address 7 8 9 0 0 1 2 1 2 3 4 5 6 A B C D E F DBF DBF3 DBF2 DBF1 DBF0 Row address 3 4 5 6 7 P0E0 to P0E3 AR3 AR2 AR1 AR0 WR BANK IXH System register P0D0 to P0D3 P0C0 to P0C3 P1B0 P0B0 to P0B3 P1A0 P0A0 to P0A3 IXM IXL RPH RPL PSW Data Sheet U15002EJ1V0DS 81 Note PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Figure 12-1. Register Files (2/2) Column Address Row Address Bit 3 0 Bit 2 Bit 1 Bit 0 Bit 3 1 Bit 2 Bit 1 Bit 0 Bit 3 2 Bit 2 Bit 1 Bit 0 Bit 3 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 IRQ 0 0 0 8 Note 9 Note A Note B Note C Note D Note E Note F Note 0 0 0 INT 0 0 0 0 0 P 0 0 INTSEL 0 IEG 0 0 0 IPBTM 0 IP IPTM 0 0 0 0 0 0 0 0 IRQBTM 0 0 IRQTM 1 Note After reset P: When INT pin is high level, 1; when INT pin is low level, 0. Table 12-3. Peripheral Hardware Name TMC TMM NRZLTMM NRZHTMM AR Address 05H 06H 03H 04H 40H Valid Bit 8 8 8 8 16 Timer count register Timer modulo register Description Low-level timer modulo register for NRZ High-level timer modulo register for NRZ Address register 82 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 13. INSTRUCTION SET 13.1 Instruction Set Outline b15 b14 to b11 BIN. 0000 0001 0010 0011 0100 0101 0110 0111 HEX. 0 1 2 3 4 5 6 7 ADD SUB ADDC SUBC AND XOR OR INC INC MOVT BR CALL RET SYSCAL RETSK EI DI RETI PUSH POP GET PUT PEEK POKE RORC STOP HALT NOP 1000 1001 1010 1011 1100 1101 1110 1111 8 9 A B C D E F LD SKE MOV SKNE BR BR BR BR r, m r, m r, m r, m r, m r, m r, m AR IX DBF, @AR @AR @AR entryNote ADD SUB ADDC SUBC AND XOR OR m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 0 1 AR AR DBF, p p, DBF WR, rf rf, WR r s h r, m m, #n4 @r, m m, #n4 addr (Page 0) addr (Page 1) addr (Page 2) addr (Page 3) ST SKGE MOV SKLT CALL MOV SKT SKF m, r m, #n4 m, @r m, #n4 addr m, #n4 m, #n m, #n Note PD17244, 17245, 17246 only Data Sheet U15002EJ1V0DS 83 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 13.2 Legend AR: ASR: addr: BANK: CMP: CY: DBF: entry: h: INTEF: INTR: INTSK: IX: MP: MPE: m: mR: mC: n: n4: PAGE: PC: p: pH: pL: r: rf: rfR: rfC: SP: s: WR: (x): Address register Address stack register specified by stack pointer Program memory address (lower 11 bits) Bank register Compare flag Carry flag Data buffer Entry address of system segment Halt releasing condition Interrupt enable flag Register automatically saved to stack in case of interrupt Interrupt stack register Index register Data memory row address pointer Memory pointer enable flag Data memory address specified by mR, mC Data memory row address (high) Data memory column address (low) Bit position (4 bits) Immediate data (4 bits) Page (bits 11 and 12 of program counter) Program counter Peripheral address Peripheral address (higher 3 bits) Peripheral address (lower 4 bits) General register column address Register file address Register file row address (higher 3 bits) Register file column address (lower 4 bits) Stack pointer Stop releasing condition Window register Contents addressed by x 84 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 13.3 List of Instructions Group Mnemonic Operand Operation Opcode Add ADD r, m m, #n4 ADDC r, m m, #n4 INC AR IX Subtract SUB r, m m, #n4 SUBC r, m m, #n4 Logical OR r, m m, #n4 AND r, m m, #n4 XOR r, m m, #n4 Judge SKT SKF Compare SKE SKNE SKGE SKLT Rotate RORC m, #n m, #n m, #n4 m, #n4 m, #n4 m, #n4 r (r) (r) + (m) (m) (m) + n4 (r) (r) + (m) + CY (m) (m) + n4 + CY AR AR + 1 IX IX + 1 (r) (r) - (m) (m) (m) - n4 (r) (r) - (m) - CY (m) (m) - n4 - CY (r) (r) 00000 10000 00010 10010 00111 00111 00001 10001 00011 10011 00110 10110 00100 10100 00101 10101 11110 11111 01001 01011 11001 11011 00111 mR mR mR mR 000 000 mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR 000 Instruction Code Operand mC mC mC mC 1001 1000 mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC 0111 r n4 r n4 0000 0000 r n4 r n4 r n4 r n4 r n4 n n n4 n4 n4 n4 r (m) (m) (m) n4 (r) (r) (m) (m) (m) n4 (r) (r) (m) (m) (m) n4 n = n, then skip CMP 0, if (m) n = 0, then skip CMP 0, if (m) (m) - n4, skip if zero (m) - n4, skip if not zero (m) - n4, skip if not borrow (m) - n4, skip if borrow CY (r)b3 (r)b2 (r)b1 (r)b0 Transfer LD ST MOV r, m m, r @r, m (r) (m) (m) (r) if MPE = 1 : (MP, (r)) (m) if MPE = 0 : (BANK, mR, (r)) (m) if MPE = 1 : (m) (MP, (r)) if MPE = 0 : (m) (BANK, mR, (r)) (m) n4 SP SP - 1, ASR PC, PC AR DBF (PC), PC ASR, SP SP + 1 01000 11000 01010 mR mR mR mC mC mC r r r m, @r 11010 mR mC r m, #n4 MOVT DBF, @AR 11101 00111 mR 000 mC 0001 n4 0000 Data Sheet U15002EJ1V0DS 85 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Group Mnemonic Operand Operation Opcode Transfer PUSH POP PEEK POKE GET PUT Branch BR AR AR WR, rf rf, WR DBF, p p, DBF addr @AR Subroutine CALL addr SP SP - 1, ASR AR AR ASR, SP SP + 1 WR (rf) (rf) WR (DBF) (p) (p) (DBF) Note 1 PC AR SP SP - 1, ASR PC, PC10-0 addr, PAGE 0 SP SP - 1, ASR PC, PC AR SP SP - 1, ASR PC, SGR 1, PC12,11 0, PC10-8 entryH, PC7-4 0, PC3-0 entryL PC ASR, SP SP + 1 PC ASR, SP SP + 1 and skip PC ASR, INTR INTSK, SP SP + 1 INTEF 1 INTEF 0 s h STOP HALT No operation 00111 00111 00111 00111 00111 00111 Note 1 00111 11100 000 000 000 rfR rfR pH pH Instruction Code Operand 1101 1100 0011 0010 1011 1010 addr 0100 addr 0000 0000 0000 rfC rfC pL pL @AR SYSCALNote 2 00111 000 0101 0000 entry 00111 entryH 0000 entryL RET RETSK RETI Interrupt EI DI Other STOP HALT NOP 00111 00111 00111 00111 00111 00111 00111 00111 000 001 100 000 001 010 011 100 1110 1110 1110 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 s h 0000 Notes 1. The operation and operation codes "BR addr" of the PD17240, 17241, 17242, 17243, 17244, 17245, and 17246 are as follows. (a) PD17240 Operand addr Operation PC10-0 addr Opcode 01100 (b) PD17241 Operand addr Operation PC10-0 addr, Page 0 PC10-0 addr, Page 1 Opcode 01100 01101 (c) PD17242 Operand addr Operation PC10-0 addr, Page 0 PC10-0 addr, Page 1 PC10-0 addr, Page 2 Opcode 01100 01101 01110 86 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 (d) PD17243, 17244, 17245, 17246 Operand addr Operation PC10-0 addr, Page 0 PC10-0 addr, Page 1 PC10-0 addr, Page 2 PC10-0 addr, Page 3 Opcode 01100 01101 01110 01111 2. PD17244, 17245, and 17246 only 13.4 Assembler (RA17K) Embedded Macro Instructions Legend flag n: FLG type symbol n: < Bit number >: Contents in < Mnemonic Embedded macro SKTn SKFn SETn CLRn NOTn > can be omitted Operand flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n Operation if (flag 1) to (flag n) = all "1", then skip if (flag 1) to (flag n) = all "0", then skip (flag 1) to (flag n) 1 (flag 1) to (flag n) 0 if (flag n) = "0", then (flag n) 1 if (flag n) = "1", then (flag n) 0 if description = NOT flag n, then (flag n) 0 if description = flag n, then (flag n) 1 (BANK) n Label function-name INITFLG BANKn Expansion instruction BRX CALLX INITFLGX Data Sheet U15002EJ1V0DS 87 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 14. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Item Supply voltage Input voltage Output voltage Output current, high Note Symbol VDD VI VO IOH REM pin Conditions Ratings -0.3 to +3.8 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 Peak value rms value -36.0 -24.0 -7.5 -5.0 -22.5 -15.0 7.5 5.0 22.5 15.0 30.0 20.0 -40 to +85 -65 to +150 Unit V V V mA mA mA mA mA mA mA mA mA mA mA mA C C mW 1 pin (P0E, P1A pins) Peak value rms value Total of P0E, P1A pins Peak value rms value Output current, low Note IOL 1 pin (P0B, P0C, P0D, P0E, P1A, REM pins) Total of P0B, P0C, P0D, REM pins Total of P0E, P1A pins Peak value rms value Peak value rms value Peak value rms value Operating temperature Storage temperature Power dissipation TA Tstg Pd TA = 85C Duty 180 Note Calculate rms value by this expression: [rms value] = [Peak value] x Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 88 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Recommended Operating Ranges (TA = -40 to +85C, VDD = 2.0 to 3.6 V) Item Supply Voltage Symbol VDD1 Conditions fX = 1 MHz High-speed mode (Instruction execution time: 16 s) fX = 4 MHz High-speed mode (Instruction execution time: 4 s) fX = 8 MHz Normal mode (Instruction execution time: 4 s) High-speed mode (Instruction execution time: 2 s) RfX = fX/2 or fX RfX = 2fX Operating temperature Low-voltage detector (Mask option) Note MIN. 2.0 TYP. MAX. 3.6 Unit V VDD2 VDD3 VDD4 2.2 3.6 V Oscillation frequency fX 1.0 3.5 -40 3.5 4.0 4.0 +25 8.0 4.5 +85 32 MHz MHz C TA tCY s Note Reset if the status of VDD = 1.7 to 2.0 V lasts for 1 ms or longer. Program hang-up does not occur even if the voltage drops, until the reset function is effected. A resonator may stop oscillating before the reset function is effected if normal operation under the low voltage is not guaranteed. Caution Design the application circuit so that the RESET pin goes low when the supply voltage is less than 2.2 V. fX vs VDD (MHZ) 10 9 8 7 6 5 System clock fX (MHz) (Normal mode) 4 3 Operation guaranteed area 2 1 0.4 0 2 2.2 3 3.6 4 Supply voltage VDD (V) Remark The region indicated by the broken lines in the above figure is the guaranteed operating range in the high-speed mode. Data Sheet U15002EJ1V0DS 89 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 3.6 V) Resonator Recommended Constants Item Conditions MIN. TYP. MAX. Unit Ceramic resonator XIN XOUT Oscillation frequency (fX)Note 1 1.0 4.0 8.0 MHz Oscillation stabilization timeNote 2 After VDD reached MIN. in oscillation voltage range 4 ms Notes 1. The oscillation frequency only indicates the oscillator characteristics. 2. The oscillation stabilization time is necessary for oscillation to be stabilized after VDD application or STOP mode release. Caution When using the system clock oscillator, wire as follows in the area enclosed by the dotted lines in the above figure, to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. Do not route the wiring near a signal line through which a large current flows. * Always make the ground point of the oscillator capacitor the same potential as GND. Do not ground the capacitor to a ground pattern through which a large current flows. * Do not fetch signals from the oscillator. 90 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Recommended Oscillator Constant Ceramic resonator (TA = -40 to +85C) Recommended Oscillation Frequency Circuit Constant (pF) Voltage Range (VDD) (MHz) C1 C2 MIN. MAX. Note Note Manufacturer Part Number Remarks Murata Mfg. Co., Ltd. CSBLA1M00J58-B0 1.0 100 100 1.8 3.6 Rd = 3.3 k CSBFB1M00J58-R1 CSTLS2M00G56-B0Note CSTCC2M00G56-R0 Note 2.0 - - Rd = 1.0 k On-chip capacitor Rd = 470 On-chip capacitor On-chip capacitor CSTLS3M00G56-B0Note CSTCC3M00G56-R0Note CSTLS4M00G56-B0 CSTCR4M00G55-R0 CSTLS6M00G56-B0 CSTCR6M00G55-R0 CSTLS8M00G56-B0 CSTCC8M00G56-R0 TDK FCR3.52MC5 FCR4.0MC5 FCR4.0MSC5 FCR6.0MC5 FCR8.0MC5 Kyocera Corp. KBR-2.0MS KBR-3.0MS KBR-4.0MKE KBR-4.0MSE KBR-6.0MKC KBR-6.0MSB KBR-8.0MKC KBR-8.0MSB 3.0 4.0 6.0 8.0 3.52 4.0 4.0 6.0 8.0 2.0 3.0 4.0 - - 1.8 3.6 On-chip capacitor 68 47 - 33 68 47 - 33 - 33 - 33 1.8 3.6 - On-chip capacitor - On-chip capacitor - On-chip capacitor - 6.0 - 33 8.0 - 33 Note A limiting resistor is required when these ceramic resonators are used (refer to the following figure). When other recommended resonators are used, the limiting resistor is not necessary. XIN XOUT Rd C1 C2 Caution The oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. If the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. The internal operation conditions of the PD17240, 17241, 17242, 17243, 17244, 17245, and 17246 must be within the specifications of the DC and AC characteristics. Data Sheet U15002EJ1V0DS 91 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 DC Characteristics (TA = -40 to +85C, VDD = 2.0 to 3.6 V) Item Input voltage, high Symbol VIHI1 VIH2 VIH3 Input voltage, low VIL1 VIL2 VIL3 Input leakage current, high ILIH RESET, INT P0A, P0B, P0C, P0D P0E, P1A, P1B RESET, INT P0A, P0B, P0C, P0D P0E, P1A, P1B P0A, P0B, P0C, P0D, P0E, VIH = VDD P1A, P1B0/INT, RESET w/o pull-down resistor P0E, P1A, P1B0/INT VIL = 0 V w/o pull-up resistor 25 100 25 VOH = 1.0 V, VDD = 3 V -6 50 200 50 -13 Conditions MIN. 0.80VDD 0.70VDD 0.70VDD 0 0 0 TYP. MAX. VDD VDD VDD 0.2VDD 0.3VDD 0.3VDD 3.0 Unit V V V V V V A A k k k mA Input leakage current, low ILIL -3.0 Internal pull-up resistor R1 R2 P0E, P1A, P1B, RESET (pulled up) P0A, P0B, P0C, P0D P1A, P1B REM 100 400 100 -24 Internal pull-down resistor Output current, high R3 IOH Output voltage, high Output voltage, low VOH VOL1 VOL2 P0E, P1A, REM P0B, P0C, P0D, REM P0E, P1A RESET = Low level or STOP mode RESET pin pulled down, VDT = VDD IOH = -0.5 mA VDD-0.3 IOL = 0.5 mA IOL = 1.5 mA 0 0 1.3 1.85 VDD 0.3 0.3 3.6 2.0 V V V V V Data retention characteristics VDDDR Low-voltage detection voltage (mask option) RAM retention detection voltage Supply current VID VDT VID = VDD, RAMFLAG = 0 (RF21H.0) VDD = 3 V 10% 1.40 1.50 V IDD1 Operating mode (high-speed) fX = 1 MHz fX = 4 MHz fX = 8 MHz 0.6 0.75 0.9 0.48 0.6 0.8 0.4 0.45 0.5 2.0 1.1 1.3 1.6 0.9 1.1 1.4 0.75 0.85 0.95 20.0 5.0 mA mA mA mA mA mA mA mA mA IDD2 Operating mode (low-speed) VDD = 3 V 10% fX = 1 MHz fX = 4 MHz fX = 8 MHz IDD3 HALT mode VDD = 3 V 10% fX = 1 MHz fX = 4 MHz fX = 8 MHz IDD4 STOP mode VDD = 3 V 10% built-in POC TA = 25C A A 2.0 Note This does not include the current that flows through the internal pull-up resistors. 92 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 AC Characteristics (TA = -40 to +85C, VDD = 2.0 to 3.6 V) Item CPU clock cycle time Note Symbol tCY1 tCY2 tINTH, tINTL tRSL VDD = 2.0 to 3.6 V VDD = 2.2 to 3.6 V Conditions MIN. 3.4 1.9 20 TYP. MAX. 33 33 Unit s s s s (Instruction execution time) INT high-/low-level width RESET low-level width 10 Note The CPU clock cycle time (instruction execution time) is determined by the oscillation frequency of the resonator connected and SYSCK (RF: address 02H) of the register file. The figure below shows the CPU clock cycle time tCY vs. supply voltage VDD characteristics (refer to 4. CLOCK GENERATOR). tCY vs VDD 40 33 CPU clock cycle time tcY ( s) 10 9 8 7 6 5 4 3.4 3 Operation guaranteed area 2 1.9 1 0 1 2.2 2 3 3.6 4 Supply voltage VDD (V) Data Sheet U15002EJ1V0DS 93 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 15. APPLICATION CIRCUIT EXAMPLE P0D2 P0D3 P1B0/INT + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P1A2 P0D1 P0D0 P0C3 P0C2 P0C1 P0C0 P0B3 P0B2 P0B1 P0B0 P0A3 P0A2 P0A1 P0A0 P0E0 P0E1 P0E2 P0E3 REM VDD XOUT 3V XIN 4 MHz GND RESET P1A0 Jog shuttle P1A1 = Key matrix 8 x 9 = 72 keys 94 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 16. PACKAGE DRAWING 30-PIN PLASTIC SSOP (7.62 mm (300)) 30 16 detail of lead end F G T P 1 A 15 E L U H I J S C D M M N S B K NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 9.850.15 0.45 MAX. 0.65 (T.P.) 0.24+0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 +5 3 -3 0.25 0.60.15 S30MC-65-5A4-2 Data Sheet U15002EJ1V0DS 95 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 17. RECOMMENDED SOLDERING CONDITIONS The PD17240, 17241, 17242, 17243, 17244, 17245, and 17246 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 17-1. Surface Mounting Type Soldering Conditions PD17240MC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300)) PD17241MC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300)) PD17242MC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300)) PD17243MC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300)) PD17244MC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300)) PD17245MC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300)) PD17246MC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300)) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three times or less Recommended Condition Symbol IR35-00-3 VPS VP15-00-3 Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, WS60-00-1 Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - Partial heating Caution Do not use different soldering methods together (except for partial heating). 96 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 APPENDIX A DIFFERENCES BETWEEN PD17246 AND PD17P246 The PD17P246 is equipped with PROM to which data can be written by the user instead of the internal mask ROM (program memory) of the PD17246. Table A-1 shows the differences between the PD17246 and PD17P246. The CPU functions and internal hardware of the PD17P246, 17240, 17241, 17242, 17243, 17244, 17245, and 17246 are identical. Therefore, the PD17P246 can be used to evaluate the program developed for the PD17240, 17241, 17242, 17243, 17244, 17245, and 17246 system. Note, however, that some of the electrical specifications such as supply current and low-voltage detection voltage of the PD17P246 differ from those of the PD17240, 17241, 17242, 17243, 17244, 17245, and 17246. Table A-1. Differences Between PD17246 and PD17P246 Product Name Item Program memory PD17P246 (PD17P246M1, 17P246M2) One-time PROM 32 KB (16,384 x 16) (0000H to 3FFFH) Mask ROM PD17246 Data memory Capacitor for oscillator Low-voltage detectorNote 1 VPP pin, operation mode select pin Instruction execution time Supply voltage Package Note 2 Note 2 447 x 4 bits * Not provided (PD17P246M1) * Provided (PD17P246M2) Provided Provided 4 s (VDD = 2.2 to 3.6 V) VDD = 2.2 to 3.6 V 30-pin plastic SSOP (7.62 mm (300)) Any (mask option) Not provided 4 s (VDD = 2.0 to 3.6 V) VDD = 2.0 to 3.6 V Any (mask option) Notes 1. Although the circuit configuration is identical, the electrical characteristics differ depending on the product. 2. When fx = 4 MHz and high-speed mode operation is set. Data Sheet U15002EJ1V0DS 97 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 APPENDIX B DEVELOPMENT TOOLS The following development tools are available to develop the programs for the PD17246 Subseries. Hardware Name In-circuit emulator IE-17K, IE-17K-ETNote 1 Remarks The IE-17K and IE-17K-ET are in-circuit emulators used in common with the 17K Series microcontrollers. The IE-17K and IE-17K-ET are connected to the PC-9800 series or IBM PC/ATTM compatible machines as the host machine via RS-232C. By using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. A higher level debugging environment can be provided by using the human interface SIMPLEHOST TM. This is an EM board for the PD17246 Subseries. It can be used alone to evaluate a system or in combination with an in-circuit emulator for debugging. The EP-17K30GS is an emulation probe for a 17K Series 30-pin shrink SOP (MC-5A4). When used with the EV-9500GT-30Note 3, it connects an EM board to the target system. The EV-9500GT-30 is a conversion adapter for a 30-pin shrink SOP (MC-5A4). It is used to connect the EP-17K30GS and target system. The AF-9706, AF-9708, and AF-9709 are PROM programmers corresponding to the PD17P246. By connecting the program adapter PA-17P236 to this PROM programmer, the PD17P246 can be programmed. The PA-17P236 is an adapter used to program the PD17P236, and is used in combination with the AF-9706, AF-9708, or AF-9709. EM board (EM-17246Note 2) Emulation probe (EP-17K30GS) Conversion adapter (EV-9500GT-30Note 3) PROM programmer (AF-9706Note 4, AF-9708Note 4, AF-9709Note 4) Program adapter (PA-17P236) Notes 1. Low-cost model: External power supply type 2. This is a product of Naito Densei Machida Mfg., Co., Ltd. (TEL +81-45-475-4191) 3. Two EV-9500GT-30 units are supplied with the EP-17K30GS. Five EV-9500GT-30 units are optionally available as a set. 4. These are products of Ando Electric Co., Ltd. (TEL: +81-53-576-1560). 98 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Software Name 17K assembler (RA17K) Outline The RA17K is an assembler common to 17K Series products. When developing the programs of devices, RA17K is used in combination with a device file (AS17225). The AS17246 is a device file for the PD17240, 17241, 17242, 17243, 17244, 17245, and 17246, and is used in combination with an assembler for the 17K Series (RA17K). Host Machine PC-9800 series IBM PC/AT compatible machine OS Japanese Windows TM Supply 3.5" 2HD Order Code SAA13RA17K SAB13RA17K SBB13RA17K Japanese Windows 3.5" 2HC English Windows Device file (AS17246) PC-9800 series IBM PC/AT compatible machine Japanese Windows 3.5" 2HD SAA13AS17246 SAB13AS17246 SBB13AS17246 Japanese Windows 3.5" 2HC English Windows Support software (SIMPLEHOST) SIMPLEHOST is a software package that enables a human interface on Windows when a program is developed by using an in-circuit emulator and a personal computer. PC-9800 series IBM PC/AT compatible machine Japanese Windows 3.5" 2HD SAA13ID17K SAB13ID17K SBB13ID17K Japanese Windows 3.5" 2HC English Windows Data Sheet U15002EJ1V0DS 99 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 100 Data Sheet U15002EJ1V0DS PD17240, 17241, 17242, 17243, 17244, 17245, 17246 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics America, Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65 03 01 Fax: 0211-65 03 327 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 Fax: 091-504 28 60 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Fax: 6250-3583 J02.11 Data Sheet U15002EJ1V0DS 101 PD17240, 17241, 17242, 17243, 17244, 17245, 17246 SIMPLEHOST is a trademark of NEC Electronics Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of IBM Corporation. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of January, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 |
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